844441 Datasheet, PDF (10/15 Pages) Integrated Device Technology – FemtoClock SAS/ SATA Clock Generator

844441 Datasheet
P l ac e o n e o f t h e 0 . 1u F by p as s ca p s d i re c tl y ad j ac e n t t o o n e o f t h e V D D p in s .
C13
0.1uF
U7
VDD
C4 C11
0.1uF _10uF
FB2
2.5V
2
1
BLM18BB221SN1
C10
0.1uF
SSC_SEL0
SSC_SEL1
F_SEL0
F_SEL1
nPLL_SEL
,'7^F^O^X⁶⁰³^-2⁵&^-1U⁷\³V^cW^ryD^sO^tal
R19 0
XTAL_IN
25 M H z( 1 2 pf )
4
X1
1
3
2
XTAL_OUT
4
8 ^SSC_SEL0
SSC_SEL1
10
16 ^F_SEL0
F_SEL1
14
nPLL_SEL
3
XTA L_IN
2
XTA L_OUT
C1
14pF
C2
14pF
Logi c Input P in Examples
Set Logic
Set Logic
VDD _{Input to '1'} VDD _{Input to '0'}
RU3
1K
To Logic
Inpu t
pins
RD4
Not Ins tall
RU4
Not Install
To Logic
In put
pins
RD3
1K
12
Q
13
nQ
5
nc ₆
nc ₇
nc
Zo = 50 Ohm
Q
R2
+
100
nQ
Zo = 50 Ohm
-
Zo = 50 Ohm
Q
R5
50
+
C12
0.1uF
-
R6
50
Zo = 50 Ohm
nQ
Alternate LVDS Termination
Figure 3B. 844441 Schematic Example
©2016 Integrated Device Technology, Inc.
10
Revison E, November 2, 2016