842023 Datasheet, PDF (9/15 Pages) Integrated Device Technology – Femtoclock™ Crystal-to-HSTL Clock Generator

842023 DATA SHEET
Termination for HSTL Outputs
VDDO
Zo = 50
Zo = 50
HSTL
R1
50
ICS HiPerClockS
HSTL Driv er
VDD
+
-
R2
50
HSTL
Figure 4. HSTL Output Termination
Schematic Example
Figure 5 shows an example of the 842023 application schematic.
In this example, the device is operated at V_DD = 3.3V. The 18pF
parallel resonant 25MHz crystal is used. The C1 = 22pF and C2 =
22pF are recommended for frequency accuracy. For different
board layouts, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy. An example of HSTL termination is
shown in this schematic.
Note: Thermal pad (E-pad) must be connected to ground (GND).
VDD
R1
VDD
10
VDDA
C4
0.1u
C5
10u
C2
22pF
X1
25MH₁ z_{8 p F}
C1
22pF
U1
1
2
3
4
VDDA
GND
XTAL_OUT
XTAL_IN
ICS842023
VDD
VDD
VDD
Q
nQ
8
7
6
5
OE
C3
0.1uF
OE
VDD=3.3V
Zo = 50 Ohm
Zo = 50 Ohm
R2
50
+
-
R3
50
Logic Control Input Examples
Set Logic
VDD _{Input to}
'1'
RU1
1K
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
Figure 5. 842023 Schematic Example
Rev A 8/14/15
9
FEMTOCLOCK™ CRYSTAL-TO-HSTL CLOCK GENERATOR