842023 Datasheet, PDF (11/15 Pages) Integrated Device Technology – Femtoclock™ Crystal-to-HSTL Clock Generator

3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 6.
V_DD
Q1
V_OUT
RL
50Ω
842023 DATA SHEET
Figure 6. HSTL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V_{OH_MAX} /R_L) * (V_{DD_MAX} - V_{OH_MAX})
Pd_L = (V_{OL_MAX} /R_L) * (V_{DD_MAX} - V_{OL_MAX})
Pd_H = (1.8V/50) * (3.465 - 1.8V) = 59.94mW
Pd_L = (0.6V/50) * (3.465 - 0.6V) = 34.38mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 94.32mW
Rev A 8/14/15
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FEMTOCLOCK™ CRYSTAL-TO-HSTL CLOCK GENERATOR