842023 Datasheet, PDF (8/15 Pages) Integrated Device Technology – Femtoclock™ Crystal-to-HSTL Clock Generator

842023 DATA SHEET
Application Information
Crystal Input Interface
The 842023 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 1 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
X1
18pF Parallel Crystal
C1
22pF
XTAL_IN
C2
22pF
XTAL_OUT
Figure 1. Crystal Input Interface
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform-
ance, power supply isolation is required. The 842023 provides
separate power supplies to isolate any high switching noise from
the outputs to the internal PLL. V_DD and V_DDA should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 3
illustrates this for a generic V_DD pin and also shows that V_DDA
requires that an additional 10 resistor along with a 10F bypass
capacitor be connected to the V_DDA pin.
3.3V or 2.5V
VDD
.01µF _10Ω
VDDA
.01µF
10µF
Figure 3. Power Supply Filtering
FEMTOCLOCK™ CRYSTAL-TO-HSTL CLOCK GENERATOR
8
Rev A 8/14/15