DAC1627D1G25 Datasheet, PDF (80/81 Pages) NXP Semiconductors – Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and x8 interpolating

Integrated Device Technology
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
17. Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 3. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 4. Thermal characteristics . . . . . . . . . . . . . . . . . . .7
Table 5. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 6. Read or Write mode access description . . . . .19
Table 7. Number of bytes to be transferred . . . . . . . . . .19
Table 8. SPI timing characteristics . . . . . . . . . . . . . . . .20
Table 9. Input LVDS bus swapping . . . . . . . . . . . . . . . .22
Table 10. Folded and interleaved format mapping . . . . . .23
Table 11. CDI mode 0: operating modes examples . . . .29
Table 12. CDI mode 1: operating modes examples . . . .29
Table 13. CDI mode 2: operating modes examples . . . .30
Table 14: Interpolation filter coefficients . . . . . . . . . . . . .31
Table 15. Complex modulator operation mode . . . . . . . .34
Table 16. Inversion filter coefficients . . . . . . . . . . . . . . . .35
Table 17. DAC transfer function . . . . . . . . . . . . . . . . . . .41
Table 18. Digital offset adjustment . . . . . . . . . . . . . . . . .42
Table 19. Auxiliary DAC transfer function . . . . . . . . . . . .44
Table 20. SPI start-up sequence . . . . . . . . . . . . . . . . . . .50
Table 21. Page_00 register allocation map . . . . . . . . . . .52
Table 22. Register COMMON (address 00h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 23. Register TXCFG (address 01h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 24. Register PLLCFG (address 02h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 25. NCO frequency registers (address 04h to 08h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 26. DAC output phase correction registers
(address 09h to 0Ah) bit description . . . . . . . .56
Table 27. Digital gain control registers (address 0Bh to 0Eh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 28. Register DAC_OUT_CTRL (address 0Fh) . . .57
Table 29. Register DAC_CLIPPING (address 10h) . . . . .57
Table 30. Digital offset value registers (address 11h to 14h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 31. NCO phase offset registers (address 15h to 16h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 32. Analog gain control (address 17h to 1Ah)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 33. Auxiliary DAC registers (address 1Bh to 1Eh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 34. SPI_PAGE register (address 1Fh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 35. Page 1 register allocation map . . . . . . . . . . . .59
Table 36. MDS_MAIN register (address 00h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 37. MDS window time registers (address 01h to 02h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 38. MDS_MISCCNTRL0 register (address 03h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 39. MDS_MAN_ADJUSTDLY register (address 04h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 40. MDS_AUTO_CYCLES register (address 05h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 41. MDS_MISCCNTRL1 register (address 06h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 42. MDS_OFFSET_DLY register (address 07h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 43. MDS_ADJDELAY register (address 08h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 44. MDS status registers (address 09h to 0Ah)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 45. Interrupt control register (address 0Bh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 46. Interrupt enable register (address 0Ch)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 47. INTR_FLAGS register (address 0Dh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 48. Bias current control registers (address 0Eh to 15h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 49. Bias current control table . . . . . . . . . . . . . . . . 66
Table 50. DAC_PON_SLEEP register (address 16h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 51. DAC_TEST_8 register (address 17h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 52. SPI_PAGE register (address 1Fh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 53. Page_0A register allocation map . . . . . . . . . . 69
Table 54. Register MAIN_CNTRL (address 00h) . . . . . . 71
Table 55. Register MAN_LDCLKDEL (address 01h) . . . 71
Table 56. Register DBG_LVDS (address 02h) . . . . . . . . 71
Table 57. Extension time reset registers
(address 04h to 05h) bit description . . . . . . . . 71
Table 58. Register DCSMU_PREDIV (address 06h) . . . 72
Table 59. LSB/MSB of polarity registers
(address 08h to 09h) bit description . . . . . . . . 72
Table 60. Register LD_CNTRL (address 0Ah) . . . . . . . . 72
Table 61. Register MISC_CNTRL (address 0Bh) . . . . . . 73
Table 62. LDS/MDS of I/Q DC levels registers
(address 0Ch to 0Fh) bit description . . . . . . . . 73
Table 63. Register IO_MUX0 and IO_MUX2
(address 10h and 12h) . . . . . . . . . . . . . . . . . . 74
Table 64. Register IO_MUX1 and IO_MUX2
(address 11h and 12h) . . . . . . . . . . . . . . . . . . 74
Table 65. Register TYPE_ID (address 1Bh) . . . . . . . . . . 75
Table 66. Register DAC_VERSION (address 1Ch) . . . . 75
Table 67. Register DIG_VERSION (address 1Dh) . . . . . 75
Table 68. Register LVDS_VERSION (address 1Eh) . . . . 75
Table 69. Register PAGE_ADD (address 1Fh) . . . . . . . . 75
Table 70. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 71. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 79
DAC1627D1G25 3
Data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
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