DAC1627D1G25 Datasheet, PDF (71/81 Pages) NXP Semiconductors – Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and x8 interpolating

Integrated Device Technology
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
11.22.8 Page A bit definition detailed description
The tables in this section contain detailed descriptions of the page A registers.
Table 54. Register MAIN_CNTRL (address 00h)
Default values are shown highlighted.
Bit Symbol
Access Value Description
4 LD_PD
R/W
LVDS interface power-down (control possible only when PD_CNTRL = 1)
0
switched on
1
switched off
3 PD_CNTRL R/W
power-down modes controlled by
0
DCMSU block
1
SPI registers
2 CAL_CNTRL R/W
compensation delay controlled by
0
DCMSU block (automatic calibration)
1
SPI registers (manual control)
1 RST_DCLK R/W
reset DCLK
0
disable
1
enable
0 RST_LCLK R/W
reset LVDS clock
0
disable
1
enable
Table 55. Register MAN_LDCLKDEL (address 01h)
Default values are shown highlighted.
Bit Symbol
Access Value Description
3 to 0 LDCLK_DEL[3:0] R/W
LVDS clock compensation delay (control only if CAL_CNTRL = 1)
-
4-bit compensation delay for LVDS clock
Table 56. Register DBG_LVDS (address 02h)
Default values are shown highlighted.
Bit Symbol
Access Value Description
3
SBER
R/W
simple BER control
0
no action
1
simple BER active
2 to 0 RESERVED R/W
000 reserved
Table 57. Extension time reset registers (address 04h to 05h) bit description
Default values are shown highlighted.
Address Register
Bit Symbol
Access Value
04h
RST_EXT_LCLK 7 to 0 RST_EXT_LCLK_TIME[7:0] R/W
-
05h
RST_EXT_DCLK 7 to 0 RST_EXT_DCLK_TIME[7:0] R/W
-
Description
specifies extension time reset,
expressed in LVDS clock period
8 bits for the extension time reset
specifies extension time reset,
expressed in DCLK period
8 bits for the extension time reset
DAC1627D1G25 3
Data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
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