DAC1627D1G25 Datasheet, PDF (1/81 Pages) NXP Semiconductors – Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and x8 interpolating

DAC1627D1G25
Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and
x8 interpolating
Rev. 03 — 2 July 2012
Data sheet
1. General description
The DAC1627D1G25 is a high-speed 16-bit dual channel Digital-to-Analog Converter
(DAC). It incorporates selectable 2, 4 and 8 interpolation filters optimized for
multi-carrier and broadband wireless transmitters at sample rates of up to 1.25 Gsps. The
DAC1627D1G25 is supplied by two power supplies and integrates a differential scalable
output current up to 34 mA.
The DAC1627D1G25 meets multi-carrier Global System for Mobile communications
(GSM) specifications. For example, with an NCO frequency of 153.6 MHz and a DAC
clock frequency of 1.2288 Gsps the full-scale dynamic range is:
• SFDR_RBW = 91 dBc (bandwidth = 180 MHz)
• IMD3 = 85 dBc
The Serial Peripheral Interface (SPI) provides full control of the DAC1627D1G25.
The DAC1627D1G25 integrates a Low Voltage Differential Signaling (LVDS) Double Data
Rate (DDR) receiver interface, with an on-chip 100  termination. The LVDS DDR
interface accepts a multiplex input data stream such as interleaved or folded. An internal
LVDS input auto-calibration ensures the robustness and stability of the interface.
Digital on-chip modulation converts the complex I and Q inputs from baseband to IF. A
40-bit Numerically Controlled Oscillator (NCO) sets the mixer frequency. High resolution
internal gain, phase and offset control provide outstanding image and Local Oscillator
(LO) signal rejection at the system analog modulator output.
An inverse (sin x) / x function ensures a controlled flatness 0.5 dB for high bandwidths at
the DAC output.
Multiple Device Synchronization (MDS) allows synchronization of the outputs of multiple
DAC devices. MDS guarantees a maximum skew of one output clock period between
several devices.
The DAC1627D1G25 includes a low noise capacitor-free integrated Phase-Locked Loop
(PLL) multiplier which generates a DAC clock rate from the LVDS clock rate.
The DAC1627D1G25 is available in an HVQFN72 package (10 mm  10 mm).
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