DAC1627D1G25 Datasheet, PDF (67/81 Pages) NXP Semiconductors – Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and x8 interpolating

Integrated Device Technology
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 49. Bias current control table …continued
BIAS[3:0]
Deviation from nominal current
1011
+20 %
1100
+25 %
1101
+30 %
1110
+35 %
1111
+40 %
Table 50. DAC_PON_SLEEP register (address 16h) bit description
Default values are shown highlighted.
Bit Symbol
Access Value Description
7 DAC_B_PON
R/W
-
DAC B power control
0
power-down
1
power on
6 DAC_B_SLEEP
R
DAC B mode selection
0
normal operation
1
Sleep mode
5 DAC_B_COM_PD R
commutator B control
0
disable (power-down)
1
enable
4 DAC_B_BLEED_PD R
DAC B bleed current control
0
disable (power-down)
1
enable
3 DAC_A_PON
R
DAC A power control
0
power-down
1
power on
2 DAC_A_SLEEP
R
DAC B mode selection
0
normal operation
1
Sleep mode
1 DAC_A_COM_PD R
commutator A control
0
disable (power-down)
1
enable
0 DAC_A_BLEED_PD R
DAC A bleed current control
0
disable (power-down)
1
enable
Table 51. DAC_TEST_8 register (address 17h) bit description
Default values are shown highlighted.
Bit Symbol
Access Value Description
2 to 0 PLL_DIG_DELAY[2:0] R/W
-
digital clock delay offset of PLL/CKGEN_DIV8
DAC1627D1G25 3
Data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
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