MC88LV926EGR2 Datasheet, PDF (8/11 Pages) Integrated Device Technology – Low Skew CMOS PLL 68060 Clock Driver

MC88LV926
Low Skew CMOS PLL 68060 Clock Driver
NETCOM
NOTES CONCERNING LOOP FILTER AND
BOARD LAYOUT ISSUES
1. Figure 7 shows a loop filter and analog isolation
scheme which will be effective in most applications. The
following guidelines should be followed to ensure stable
and jitter-free operation:
1a. All loop filter and analog isolation components should
be tied as close to the package as possible. Stray
current passing through the parasitics of long traces can
cause undesirable voltage transients at the RC1 pin.
1b. The 47 Ω resistors, the 10 μF low frequency bypass
capacitor, and the 0.1 μF high frequency bypass
capacitor form a wide bandwidth filter that will make the
88LV926 PLL insensitive to voltage transients from the
system digital V_CC supply and ground planes. This filter
will typically ensure that a 100mV step deviation on the
digital V_CC supply will cause no more than a 100 ps
phase deviation on the 88LV926 outputs. A 250 mV
step deviation on V_CC using the recommended filter
values will cause no more than a 250 ps phase
deviation; if a 25 μF bypass capacitor is used (instead of
10 μF) a 250 mV V_CC step will cause no more than a
100 ps phase deviation.
If good bypass techniques are used on a board design
near components which may cause digital V_CC and
ground noise, the above described V_CC step deviations
should not occur at the 88LV926's digital V_CC supply.
The purpose of the bypass filtering scheme shown in
Figure 6 is to give the 88LV926 additional protection
from the power supply and ground plane transients that
can occur in a high frequency, high speed digital system.
1c. There are no special requirements set forth for the loop
filter resistors (470 K and 33 0Ω). The loop filter
capacitor (0.1uF) can be a ceramic chip capacitor, the
same as a standard bypass capacitor.
1d. The 470 K reference resistor injects current into the
internal charge pump of the PLL, causing a fixed offset
between the outputs and the SYNC input. This also
prevents excessive jitter caused by inherent PLL dead–
band. If the VCO (2X_Q output) is running above
40 MHz, the 470 K resistor provides the correct amount
of current injection into the charge pump (2–3 μA). If the
VCO is running below 40 MHz, a 1 MΩ reference
resistor should be used (instead of 470 K).
2. In addition to the bypass capacitors used in the analog
filter of Figure 7, there should be a 0.1 μF bypass
capacitor between each of the other (digital) four V_CC
pins and the board ground plane. This will reduce output
switching noise caused by the 88LV926 outputs, in
addition to reducing potential for noise in the ‘analog'
section of the chip. These bypass capacitors should
also be tied as close to the 88LV926 package as
possible.
NOTE: Further loop optimization may occur.
10 μF Low
Freq Bias
0.1 μF High
Freq Bias
Board V_CC
47 Ω
470 KΩ or
1 MΩ
47 Ω
5 Analog V_CC
330 Ω
0.1 μF (Loop Filter
Cap)
6 RC1
7 Analog GND
Analog Loop Filter/VCO Section
of the MC88LV926 20-Pin SOIC
Package (not drawn to scale)
Board GND
A separate Analog power suppy is not necessary and should not be used.
Following these prescribed guidelines is all that is necessary to use the
MC88LV926 in a normal digital environment.
Figure 7. Recommended Loop Filter and Analog Isolation Scheme for the MC88LV926
IDT™ Lo^Mw ^CS⁸ke⁸w^LVC⁹M²O⁶S PLL 68060 Clock Driver
MC88LV926
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