MC88LV926EGR2 Datasheet, PDF (4/11 Pages) Integrated Device Technology – Low Skew CMOS PLL 68060 Clock Driver

MC88LV926
Low Skew CMOS PLL 68060 Clock Driver
NETCOM
RST_OUT
RST_IN
SYNC1
Lock Indicator
RESET_OUT
PFD
CH
PUMP
VCO
PLL_EN
0
1
÷8
Power–On
Reset
MR
Delay
Q
2X_Q
÷2
R
Q
Q0
÷4
R
Q
Q1
÷4
R
Q
Q2
÷4
R
Q
Q3
÷4
R
CLKEN
÷4
R
Figure 2. MC88LV926 Logic Block Diagram
Table 5. Sync Input Timing Requirements
Symbol
t_RISE/FALL
SYNC Input
t_CYCLE,
SYNC Input
Parameter
Rise/Fall Time, SYNC Input
From 0.8V to 2.0V
Input Clock Period
SYNC Input⁽¹⁾
Duty Cycle
Duty Cycle, SYNC Input
1. When V_CC > 4.0 volts, Maximum SYNC Input Period is 125 ns.
Minimum
–
Maximum
5.0
1
f_{2X_Q}/4
200⁽¹⁾
50% ± 25%
Unit
ns
ns
IDT™ Lo^Mw ^CS⁸ke⁸w^LVC⁹M²O⁶S PLL 68060 Clock Driver
MC88LV926
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Freescale Semiconductor