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MC88LV926EGR2 Datasheet, PDF (5/11 Pages) Integrated Device Technology – Low Skew CMOS PLL 68060 Clock Driver | |||
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MC88LV926
Low Skew CMOS PLL 68060 Clock Driver
NETCOM
Table 6. Frequency Specifications (TA = 0°C to 70°C; VCC = 3.3 V ± 0.3 V
Symbol
Parameter
Guaranteed Minimum
Fmax (2X_Q) Maximum Operating Frequency, 2X_Q Output
66
Fmax (âQ')
Maximum Operating Frequency,
33
Q0âQ3 Outputs
NOTE: Maximum Operating Frequency is guaranteed with the 88LV926 in a phase-locked condition.
Unit
MHz
MHz
Table 7. AC Characteristics (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V
Symbol
Parameter
Minimum
tRISE/FALL
Rise/Fall Time, into 50Ω Load
0.3
All Outputs
tRISE/FALL
Rise/Fall Time into a 50Ω Load
0.5
2X_Q Output
tpulse
(1)
width(a)
(Q0, Q1, Q2, Q3)
tpulse
(1)
width(b)
(2X_Q Output)
tSKEWr(2)
(Rising)
Output Pulse Width
Q0, Q1, Q2, Q3 at 1.65V
Output Pulse Width
2X_Q at 1.65V
OutputâtoâOutput Skew
Between Outputs Q0âQ2
(Rising Edge Only)
0.5tcycle â 0.5
0.5tcycle â 0.5
â
tSKEWf(2)
OutputâtoâOutput Skew
â
(Falling)
Between Outputs Q0âQ2
(Falling Edge Only)
tSKEWall(2)
OutputâtoâOutput Skew
â
2X_Q, Q0âQ2, Q3
tSKEW QCLKEN(1) OutputâtoâOutput Skew
(2)
QCLKEN to 2X_Q 2X_Q = 50 MHz
2X_Q = 66 MHz
tLOCK(4)
tPHL MR â Q(1)
PhaseâLock Acquisition Time,
All Outputs to SYNC Input
Propagation Delay,
MR to Any Output (HighâLow)
tREC, MR to
SYNC(1)(5)
Reset Recovery Time rising MR edge to
falling SYNC edge(6)
tW, MR LOW(1) (5) Minimum Pulse Width, MR input Low
tW, RST_IN
LOW(1)
Minimum Pulse Width, RST_IN Low
tPZL(1)
Output Enable Time
RST_IN Low to RST_OUT Low
tPLZ(1)
Output Enable Time
RST_IN High to RST_OUT High Z
9.7(3)
7.0(3)
1
1.5
9
5
10
1.5
1016 âQ' Cycles
(508 Q/2 Cycles)
Maximum
1.6
1.6
0.5tcycle + 0.5
0.5tcycle + 0.5
500
1.0
750
â
Unit
Condition
ns tRISE â 0.8 V to 2.0 V
tFALL â 2.0 V to 0.8 V
ns tRISE â 0.8 V to 2.0 V
tFALL â 2.0 V to 0.8 V
ns 50 Ω Load Terminated to VCC/
2 (See Application Note 3)
ns 50 Ω Load Terminated to VCC/
2 (See Application Note 3)
ps Into a 50Ω Load Terminated to
VCC/2 (See Timing Diagram in
Figure 6)
ns Into a 50 Ω Load Terminated to
VCC/2 (See Timing Diagram in
Figure 6)
ps Into a 50 Ω Load Terminated to
VCC/2 (See Timing Diagram in
Figure 6)
ns Into a 50 Ω Load Terminated to
VCC/2 (See Timing Diagram in
Figure 6)
10
ms
13.5
ns Into a 50 Ω Load
Terminated to VCC/2
â
ns
â
ns
â
ns When in PhaseâLock
16.5
1024 âQ' Cycles
(512 Q/2 Cycles)
ns See Application Notes, Note 5
ns See Application Notes, Note 5
1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this
methodology.
2. Under equally loaded conditions and at a fixed temperature and voltage.
3. Guaranteed that QCLKEN will meet the setup and hold time requirement of the 68060.
4. With VCC fully poweredâon: tCLOCK Max is with C1 = 0.1 μF; tLOCK Min is with C1 = 0.01 μF.
5. Specification is valid only when the PLL_EN pin is low.
6. See Application Notes, Note 4 for the distribution in time of each output referenced to SYNC.
IDT⢠Low Skew CMOS PLL 68060 Clock Driver
FreescalAedTviamnicnegdSCollouctikonDsrivOerrgsanDiezvaitcioenDhaatsa been acquired by Integrated Device Technology, Inc
Freescale Semiconductor
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MC88LVM92C688LV926
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