MC88LV926EGR2 Datasheet, PDF (6/11 Pages) Integrated Device Technology – Low Skew CMOS PLL 68060 Clock Driver

MC88LV926
Low Skew CMOS PLL 68060 Clock Driver
NETCOM
APPLICATION NOTES
1. Statistical characterization techniques were used to
guarantee those specifications which cannot be
measured on the ATE. MC88LV926 units were
fabricated with key transistor properties intentionally
varied to create a 14 cell designed experimental matrix.
IC performance was characterized over a range of
transistor properties (represented by the 14 cells) in
excess of the expected process variation of the wafer
fabrication area. IC performance to each specification
and fab variation were used to set performance limits of
ATE testable specifications within those which are to be
guaranteed by statistical characterization. In this way, all
units passing the ATE test will meet or exceed the non-
tested specifications limits.
2. A 470 KΩ or 1 MΩ resistor tied to either Analog V_CC or
Analog GND, as shown in Figure 3, is required to
ensure no jitter is present on the MC88LV926 outputs.
This technique causes a phase offset between the
SYNC input and the Q0 output, measured at the pins.
The t_PD spec describes how this offset varies with
process, temperature, and voltage. The specs were
arrived at by measuring the phase relationship for the
14 lots described in note 1 while the part was in phase-
locked operation. The actual measurements were made
with a 10 MHz SYNC input (1.0 ns edge rate from 0.8 V
to 2.0 V). The phase measurements were made at
1.5 V. See Figure 3 for a graphical description.
3. Two specs (t_RISE/FALL and t_PULSE Width 2X_Q output,
see AC Specifications) guarantee that the MC88LV926
meets the 33 MHz and 66 MHz 68060 P-Clock input
specification.
External
Loop Filter
RC1
330 Ω
0.1 μF
R2
1 MΩ or 470 K Ω
C1 Reference
Resistor
Analog V_{CC RC1}
1 MΩ or 470 KΩ
Reference
Resistor
330 Ω
R2
0.1 μF
C1
Analog GND
With the 470 KΩ resistor tied in this fashion, the T_PD specification
measured at the input pins is:
t_PD = 2.25 ns ± 1.0 ns (Typical Values)
SYNC InputT
2.25 ns
Offset
Q0 OutputT
3V
5V
Analog GND
With the 470 KΩ resistor tied in this fashion, the T_PD specification
measured at the input pin is:
t_PD = –0.80 ns ± 0.30 ns
SYNC Input
Q0 Output
–0.8 ns
Offset
3V
5V
Figure 3. Depiction of the Fixed SYNC to Q0 Offset (t_PD) Which Is Present
When a 470 KΩ Resistor Is Tied to V_CC or Ground
Internal
Logic
RST_OUT Pin
V_CC
1K
C_L
Analog GND
Figure 4. RST_OUT Test Circuit
IDT™ Lo^Mw ^CS⁸ke⁸w^LVC⁹M²O⁶S PLL 68060 Clock Driver
MC88LV926
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