ICS9LPR501_09 Datasheet, PDF (8/21 Pages) Integrated Device Technology – 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR

ICS9LPR501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
Datasheet
AC Electrical Characteristics - Low Power Differential Outputs
Advance Information
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX UNITS NOTES
Rising Edge Slew Rate
tSLR
Averaging on
2.5
4
V/ns 2, 3
Falling Edge Slew Rate
tFLR
Averaging on
2.5
4
V/ns 2, 3
Slew Rate Variation
tSLVAR
Averaging on
20
% 1, 10
Differential Voltage Swing
VSWING
Averaging off
300
mV
2
Crossing Point Voltage
VXABS
Averaging off
300
550
mV 1,4,5
Crossing Point Variation
VXABSVAR
Averaging off
140
mV 1,4,9
Maximum Output Voltage
VHIGH
Averaging off
1150 mV 1,7
Minimum Output Voltage
VLOW
Averaging off
-300
mV 1,8
Duty Cycle
DCYC
Averaging on
45
55
%
2
CPU[1:0] Skew
CPUSKEW10
Differential Measurement
100
ps
1
CPU[2_ITP:0] Skew
CPUSKEW20
Differential Measurement
150
ps
1
SRC[10:0] Skew
SRCSKEW
Differential Measurement
3000
ps 1,6
NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1_{Measurement taken for single ended waveform on a component test board (not in system)}
2 _{Measurement taken from differential waveform on a component test board. (not in system)}
3 _{Slew rate emastured through V_swing voltage range centered about differential zero}
4 _{Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)}
5 _{Only applies to the differential rising edge (Clock rising, Clock# falling)}
6 _{Total distributed intentional SRC to SRC skew. Maximum allowable interpair skew is 150 ps.}
7 _{The max voltage including overshoot.}
8 _{The min voltage including undershoot.}
9 _{The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross}
induced modulation by setting C_cross_delta to be smaller than V_Cross absolute
10 _{Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising}
meets Clock# falling. The median cross point is used to calculate the voltage
Clock Jitter Specs - Low Power Differential Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
CPU Jitter - Cycle to Cycle
CPUJC2C
Differential Measurement
SRC Jitter - Cycle to Cycle
SRCJC2C
Differential Measurement
DOT Jitter - Cycle to Cycle
DOTJC2C
Differential Measurement
NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
MAX
85
125
250
UNITS NOTES
ps
1
ps
1
ps
1
1_{Jitter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system performance}
will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the receiver
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER
SYMBOL
Long Accuracy
ppm
Clock period
T_period
Absolute min/max period
T_abs
Output High Voltage
V_OH
Output Low Voltage
V_OL
Output High Current
I_OH
Output Low Current
Rising Edge Slew Rate
Falling Edge Slew Rate
Pin to Pin Skew
Intential PCI to PCI delay
Duty Cycle
Jitter, Cycle to cycle
I_OL
t_SLR
t_FLR
t_skew
t_skew
d_t1
t_jcyc-cyc
CONDITIONS
see Tperiod min-max values
33.33MHz output no spread
33.33MHz output spread
33.33MHz output no spread
33.33MHz output nominal/spread
I_OH = -1 mA
I_OL = 1 mA
V _OH @MIN = 1.0 V
V_OH@MAX = 3.135 V
V_OL @ MIN = 1.95 V
V_OL @ MAX = 0.4 V
Measured from 0.8 to 2.0 V
Measured from 2.0 to 0.8 V
V_T = 1.5 V
V_T = 1.5 V
V_T = 1.5 V
V_T = 1.5 V
IDT^TM/ICS^TM 64-pin CK505 w/Fully Integrated Voltage Regulator
8
MIN
-100
29.99700
30.08421
29.49700
29.56617
2.4
-33
30
1
1
100
45
MAX UNITS NOTES
100 ppm 1,2
30.00300 ns
2
30.23459 ns
2
30.50300 ns
2
30.58421 ns
2
V
1
0.55
V
1
mA
1
-33
mA
1
mA
1
38
mA
1
4
V/ns 1
4
V/ns 1
250
ps
2
200
ps
2
55
%
2
500
ps
2
1118M—11/24/09