ICS9LPR501_09 Datasheet, PDF (10/21 Pages) Integrated Device Technology – 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR

ICS9LPR501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
Datasheet
Advance Information
Electrical Characteristics - SE1/2=25MHz
PARAMETER
SYMBOL
CONDITIONS
Long Accuracy
ppm
see Tperiod min-max values
Clock period
Absolute min/max period
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rising Edge Slew Rate
Falling Edge Slew Rate
Duty Cycle
Jitter, Cycle to cycle
Jitter, Long Term
T_period
T_abs
V_OH
V_OL
I_OH
I_OL
t_SLR
t_FLR
d_t1
t_{j c y c -c y c}
t_LTJ
25.00MHz output nominal
25.00MHz output nominal
I_OH = -1 mA
I_OL = 1 mA
V _OH @MIN = 1.0 V
V_OH@MAX = 3.135 V
V_OL @ MIN = 1.95 V
V_OL @ MAX = 0.4 V
Measured from 0.8 to 2.0 V
Measured from 2.0 to 0.8 V
V_T = 1.5 V
V_T = 1.5 V
V_T = 1.5 V @ 10us delay
MIN
-100
39.99600
39.32360
2.4
-29
29
1
1
45
MAX UNITS NOTES
100
ppm 1,2
40.00400 ns
1
40.67640 ns
1
V
1
0.4
V
1
mA
1
-23
mA
1
mA
1
27
mA
1
4
V/ns
1
4
V/ns
1
55
%
1
500
ps
1
3000
ps
1
Table 1: CPU Frequency Select Table
FSLC²
B0b7
FSLB¹
B0b6
FSLA¹
B0b5
CPU
MHz
SRC
MHz
PCI REF
MHz MHz
0
0
0
266.66
0
0
1
133.33
0
1
0
200.00
0
1
1
166.66 100.00 33.33 14.318
1
0
0
333.33
1
0
1
100.00
1
1
0
400.00
1
1
1
Reserved
1. FS_LA and FS_LB are low-threshold inputs.Please see V_{IL_FS} and V_{IH_FS} specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_LC is a three-level input. Please see the V_{IL_FS} and V_{IH_FS}
specifications in the Input/Supply/Common Output Parameters Table for correct values.
USB
MHz
48.00
DOT
MHz
96.00
Table 2: PLL3 Quick Configuration
B1b4
B1b3
B1b2
B1b1
Pin 17
MHz
0
0
0
0
0
0
0
1
100.00
0
0
1
0
100.00
0
0
1
1
100.00
0
1
0
0
100.00
0
1
0
1
100.00
0
1
1
0
100.00
0
1
1
1
N/A
1
0
0
0
24.576
1
0
0
1
24.576
1
0
1
0
98.304
1
0
1
1
27.000
1
1
0
0
25.000
1
1
0
1
N/A
1
1
1
0
N/A
1
1
1
1
N/A
Pin 18
MHz
100.00
100.00
100.00
100.00
100.00
100.00
N/A
24.576
98.304
98.304
27.000
25.000
N/A
N/A
N/A
Spread
%
Comment
PLL 3 disabled
0.5% Down Spread
SRCCLK1 from SRC_MAIN
0.5% Down Spread
Only SRCCLK1 from PLL3
1% Down Spread
Only SRCCLK1 from PLL3
1.5% Down Spread
Only SRCCLK1 from PLL3
2% Down Spread
Only SRCCLK1 from PLL3
2.5% Down Spread
Only SRCCLK1 from PLL3
N/A
N/A
None
24.576Mhz on SE1 and SE2
None
24.576Mhz on SE1, 98.304Mhz on SE2
None
98.304Mhz on SE1 and SE2
None
27Mhz on SE1 and SE2
None
25Mhz on SE1 and SE2
N/A
N/A
N/A
N/A
N/A
N/A
IDT^TM/ICS^TM 64-pin CK505 w/Fully Integrated Voltage Regulator
1118M—11/24/09
10