ICS9LPR501_09 Datasheet, PDF (21/21 Pages) Integrated Device Technology – 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR

ICS9LPR501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
Datasheet
Revision History
Rev. Issue Date Description
1. Updated Byte 11
A 10/27/2006 2. Updated IDD to CK505 Rev 1.0 spec
B
2/9/2007 ^{1. Updated M/N programming bytes, removed the +2 and +8}
2. Added Byte 63 bit 1 for SATA PLL on/off
C
4/3/2007 Added Bytes 24-25.
D 4/17/2007 Removed SSOP Ordering Information.
E
8/8/2007 Release to Final.
F 11/6/2007 Added Foot Note on SMBus.
1. Updated PLL3 Configuration Table.
G 2/19/2008 2. Updated Power Management Table to Show Hi-z on latched inputs during PD.
H
3/7/2008 Updated Electrical Characteristics
J
12/5/2008 Added Electrical table for SE1/2-25MHz.
K
2/9/2009 Updated Electrical Characteristics
L 2/23/2009 Updated note under Byte 63 table.
M 11/24/2009 Removed references to PCIe Gen2 performance.
Page #
Various
Various
20
22
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19
11
7-9
10
Various
18
Various
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Printed in USA
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