ICS9LPR501_09 Datasheet, PDF (18/21 Pages) Integrated Device Technology – 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR

ICS9LPR501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
Datasheet
Advance Information
Byte 22 CPU M/N Programming
Bit Pin
Name
Description
Type
0
1
7
N Div bit 8
PLL 1 M/N Programming
RW
-
-
6
N Div bit 9
(Intel PLL1 CPU)
RW
-
-
5
M Div Bit 5
RW
-
-
4
M Div Bit 4
RW
-
-
3
M Div Bit 3
RW
-
-
2
M Div Bit 2
RW
-
-
1
M Div Bit 1
RW
-
-
0
M Div Bit 0
RW
-
-
Byte 23 CPU M/N Programming
Bit Pin
Name
Description
Type
0
1
7
N Div bit 7
PLL 1 M/N Programming
RW
-
-
6
N Div bit 6
(Intel PLL1 CPU)
RW
-
-
5
N Div bit 5
RW
-
-
4
N Div bit 4
RW
-
-
3
N Div bit 3
RW
-
-
2
N Div bit 2
RW
-
-
1
N Div bit 1
RW
-
-
0
N Div Bit 0
RW
-
-
Bytes 24-62 Reserved
Byte 63 Special Power Management Features (Rev P Silicon and Higher)
Bit Pin
Name
Description
RW
0
1
7
Reserved
RW
6
Reserved
RW
5
Reserved
RW
4
Reserved
RW
3
Reserved
RW
2
Reserved
RW
1
SATA PLL
Power Management Feature
RW
off
on
0
XTAL PD Control
Controls XTAL on/off in legacy PD
RW
off
on
Note: Default is "off" for Rev P Silicon and higher.
*Accessing any SMBus bytes not shown in the datasheet could result in incorrect clock functions.
Default
X
X
X
X
X
X
X
X
Default
X
X
X
X
X
X
X
X
Default
0
0
0
0
0
0
Note
1
IDT^TM/ICS^TM 64-pin CK505 w/Fully Integrated Voltage Regulator
18
1118M—11/24/09