ICS9220B Datasheet, PDF (8/16 Pages) Integrated Device Technology – Programmable RambusTM XDRTM Clock Generator

ICS9220B
Programmable Rambus^TM XDR^TMClock Generator
Device ID and SMBus Device Address
The device ID (SMB_A(2:1)) is part of the SMBus device address. The least significant bit of the address designates a write
or read operation. Table 3 shows the addresses for four ICS9220 devices on the same SMBus.
Table 3. SMBus Device Addresses
ICS 9220
Device
Operation
Hex
Address
Write
D8
0
Read
D9
Write
DA
1
Read
DB
Write
DC
2
Read
DD
Write
3
DE
Read
DF
8 bit SMBus De vice Addre ss Including Oper.
Control Function AS2
AS1
Wr#/Rd
0
0
0
1
0
0
1
1
11011
0
1
0
1
0
1
1
1
Operating Modes
Table 4: Operating Modes
Byte 1
BYPASS#/
OE
PLL
L
X
X
H
X
1
H
L
0
H
H
0
H
H
0
H
H
0
H
H
0
Notes
1 Bypass Mode
2 Power up default mode
Byte 0
ODCLK_T/C1 ODCLK_T/C0
X
X
Z
Z
X
X
Reserved for Vendor Test
X
X
CLK_INT/C
0
0
Z
Z
0
1
Z
CLK_INT/C
1
0
CLK_INT/C
Z
1
1
CLK_INT/C CLK_INT/C
IDT^TM Programmable Rambus^TM XDR^TMClock Generator
8
1427A—01/26/10