ICS9220B Datasheet, PDF (5/16 Pages) Integrated Device Technology – Programmable RambusTM XDRTM Clock Generator

ICS9220B
Programmable Rambus^TM XDR^TMClock Generator
I²C Table: Frequency Control Register
Byte 4
Pin # Name
Control Function Type
0
Bit 7
-
Reserved
Reserved
RW
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
Reserved
Reserved
RW
-
-
Reserved
Reserved
RW
-
-
Reserved
Reserved
RW
-
-
Reserved
Reserved
RW
-
-
Reserved
Reserved
RW
-
-
Reserved
Reserved
RW
-
-
Reserved
Reserved
RW
-
1
PWD
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
I²C Table: VCO Frequency Control Register
Byte 5
Pin # Name
Control Function
Bit 7
-
Reserved
Reserved
Bit 6
Bit 5
Bit 4
Bit 3
-
Reserved
Reserved
-
Reserved
Reserved
-
Reserved
Reserved
-
M DIV3
Bit 2
-
M DIV2
M Divider Programming
Bit 1
-
M DIV1
b(3:0)
Bit 0
-
M DIV0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
-
-
-
-
-
-
-
-
The decimal representation of
M and N Divider in Byte 5 and
6 will configure the PLL VCO
frequency. VCO frequency =
100 x
{[NDIV(5:0)+2]/[MDIV(3:0)+2]}
PWD
0
0
0
0
0
0
1
0
I²C Table: VCO Frequency Control Register
Byte 6
Pin # Name
Control Function
Bit 7
-
Reserved
Bit 6
-
Reserved
Bit 5
-
N DIV5
Bit 4
-
N DIV4
N Divider Programming
Bit 3
-
N DIV3
b(5:0)
Bit 2
-
N DIV2
Bit 1
-
N DIV1
Bit 0
-
N DIV0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
-
-
-
-
The decimal representation of
M and N Divider in Byte 5 and
6 will configure the PLL VCO
frequency. VCO frequency =
100 x
{[NDIV(5:0)+2]/[MDIV(3:0)+2]}
PWD
0
0
0
0
1
0
1
0
IDT^TM Programmable Rambus^TM XDR^TMClock Generator
5
1427A—01/26/10