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ICS9220B Datasheet, PDF (10/16 Pages) Integrated Device Technology – Programmable RambusTM XDRTM Clock Generator
ICS9220B
Programmable RambusTM XDRTMClock Generator
DC Characteristics - Inputs
TA = -40°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Supply Voltage
High-level input voltage
Low-level input voltage
Crossing point voltage
Difference in crossing point voltage
Input threshold voltage
High-level input voltage for single-ended
CLK_IN
VDD2.5,
AVDD
VIHCLK
VILCLK
VIXCLK
VIXCLK
VTH
VIHSE
CLK_INT, CLK_INC
Singled-ended CLK_IN1
2.375
0.6
-0.15
0.2
0.35
VTH +
0.3
Low-level input voltage for single-ended
CLK_IN
VILSE
-0.15
High-level input voltage
Low-level input voltage
High-level input voltage - SMBus
Low-level input voltage - SMBus
VIH
VIL
VIHSMB
VILSMB
OE, AS1, AS2, BYPASS#/PLL
SMBCLK, SMBDAT
1.4
-0.15
1.4
-0.15
MAX UNITS
2.625 V
0.95
V
0.15
V
0.55
V
0.15
V
0.5VDD2.5 V
2.625 V
VTH -
V
0.3
2.625 V
0.8
V
3.4652 V
0.8
V
Notes:
1 When using singled-ended clock input, VTH is supplied to CLK_INTC as shown in Figure 2. Duty cycle of
singled-ended CLK_IN is measured at VTH.
2 This range of SMBus input high voltages allows the 9220 to co-exist with 3.3V, 2.5V and 1.8V devices on
the same SMBus.
AC Characteristics-Outputs
TA = -40°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 5% (unless otherwise stated)
PARAMETER1
SYMBOL
CONDITION
MIN TYP
Short term jitter (over 1 to 6 clock cycles) tJ2
f = 400 to 635 MHz
f = 635 to 800 MHz
-
-
Cycle-to-cycle Jitter
Tjcyc-cyc
Duty cycle
DC
45
Output rise and fall times
tR, tF 20% to 80% of output voltage 140
Difference between output rise and fall
time on same pin of a single device
tR-F
20% to 80% of output voltage
-
Dynamic output impedance
ZOUT2
VOL = 0.9 V
1000
MAX
40
30
100
55
300
UNITS
ps
ps
ps
%
ps
100
ps
-
Ω
Notes:
1 Guaranteed by design and characterization, not 100% tested in production
2 Zout is defined at the output pins.
IDTTM Programmable RambusTM XDRTMClock Generator
10
1427A—01/26/10