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ICS854S1208I Datasheet, PDF (8/19 Pages) Integrated Device Technology – Eight differential LVDS output pairs
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ICS854S1208I Data Sheet
DIFFERENTIAL-TO-LVDS FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
fOUT
tPD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
tsk(pp) Part-to-Part Skew; NOTE 3, 4
tsk(b)
Bank Skew; NOTE 3, 5
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
ƒ ≤ 750MHz
tEN
Output Enable Time; NOTE 6
tDIS
Output Disable Time; NOTE 6
Minimum
0.7
55
44
Typical
Maximum
1.5
1.75
40
400
35
250
56
10
10
Units
GHz
ns
ps
ps
ps
ps
%
ns
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential cross points.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the differential cross points.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage, same temperature and with equal load
conditions. Using the same type of input on each device, the output is measured at the differential cross points.
NOTE 5: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
Table 5B. AC Characteristics, VDD = VTAP = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
fOUT
tPD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
tsk(pp) Part-to-Part Skew; NOTE 3, 4
tsk(b)
Bank Skew; NOTE 3, 5
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
ƒ ≤ 750MHz
tEN
Output Enable Time; NOTE 6
tDIS
Output Disable Time; NOTE 6
For NOTES, see Table 5A above.
Minimum
0.6
50
44
Typical
Maximum
1.5
1.8
40
400
35
275
56
10
10
Units
GHz
ns
ps
ps
ps
ps
%
ns
ns
ICS854S1208AYI REVISION A APRIL 27, 2012
8
©2012 Integrated Device Technology, Inc.
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