ICS854S1208I Datasheet, PDF (4/19 Pages) Integrated Device Technology – Eight differential LVDS output pairs

ICS854S1208I Data Sheet
DIFFERENTIAL-TO-LVDS FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
Table 1. Pin Descriptions
Number
1, 12, 18, 19, 25,
30, 36, 42, 43
2
3
4
5
6, 10, 13, 24,
31, 37, 48
7
Name
V_DD
DIV_SELA
V_TAP
CLK0
nCLK0
GND
CLK_SEL
8
9
11
14, 15
16, 17
20, 21
22, 23
26
nCLK1
CLK1
DIV_SELB
QA0, nQA0
QA1, nQA1
nQB1, QB1
nQB0, QB0
OEA0
27
OEA1
28
OEA2
29
OEA3
32
OEB3
33
OEB2
34
OEB1
35
38, 39
40, 41
44, 45
46, 47
OEB0
QB2, nQB2
QB3, nQB3
nQA3, QA3
nQA2, QA2
Type
Description
Power
Power supply pins.
Input
Power
Input
Input
Pulldown
Pulldown
Pullup/
Pulldown
Controls frequency division for QA[0:3], nQA[0:3] outputs.
LVCMOS / LVTTL interface levels.
Power supply mode. See Supply Mode Operation Table on page 1.
Non-inverting differential clock input.
Inverting differential clock input. V_DD/2 default when left floating.
Power
Power supply ground.
Input
Input
Input
Input
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Clock select input. When HIGH, selects CLK1/nCLK1 inputs. When LOW,
selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels.
Inverting differential clock input. V_DD/2 default when left floating.
Non-inverting differential clock input.
Controls frequency division for QB[0:3], nQB[0:3] outputs.
LVCMOS / LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Output enable for QA0 output pair. LVCMOS/LVTTL interface levels.
See Table 3A.
Output enable for QA1 output pair. LVCMOS/LVTTL interface levels.
See Table 3A.
Output enable for QA2 output pair. LVCMOS/LVTTL interface levels.
See Table 3A.
Output enable for QA3 output pair. LVCMOS/LVTTL interface levels.
See Table 3A.
Output enable for QB3 output pair. LVCMOS/LVTTL interface levels.
See Table 3B.
Output enable for QB2 output pair. LVCMOS/LVTTL interface levels.
See Table 3B.
Output enable for QB1 output pair. LVCMOS/LVTTL interface levels.
See Table 3B.
Output enable for QB0 output pair. LVCMOS/LVTTL interface levels.
See Table 3B.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
ICS854S1208AYI REVISION A APRIL 27, 2012
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©2012 Integrated Device Technology, Inc.