ICS854S1208I Datasheet, PDF (15/19 Pages) Integrated Device Technology – Eight differential LVDS output pairs

ICS854S1208I Data Sheet
DIFFERENTIAL-TO-LVDS FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
LVDS Power Considerations
This section provides information on power dissipation and junction temperature for the ICS854S1208I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS854S1208I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V_DD = 3.3V + 5% = 3.465V, which gives worst case results.
Max power dissipation occurs at -40°C.
Max I_DD at -40°C = 305mA
• Power_MAX = V_{DD_MAX} * I_{DD_MAX} = 3.465V * 305mA = 1056.825mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 33.1°C/W per Table 6 below.
Max I_DD at 85°C = 287.8mA.
Max power at 85°C = 3.465V * 287.8mA = 997.227mW.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.997W * 33.1°C/W = 118°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance θ_JA for 48 Lead TQFP, E-Pad, Forced Convection
θ_JA by Velocity
Meters per Second
0
1
Multi-Layer PCB, JEDEC Standard Test Boards
33.1°C/W
27.2°C/W
2.5
25.7°C/W
ICS854S1208AYI REVISION A APRIL 27, 2012
15
©2012 Integrated Device Technology, Inc.