ICS854S1208I Datasheet, PDF (3/19 Pages) Integrated Device Technology – Eight differential LVDS output pairs

ICS854S1208I Data Sheet
DIFFERENTIAL-TO-LVDS FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
Function Description
The ICS854S1208I has a glitch free input mux that is controlled by
the CLK_SEL pin. It is designed to switch between 2 input clocks
whether running or not. In the case where both clocks are running,
when CLK_SEL changes, the output clocks go low after one cycle
of the output clock (nominally). The outputs then stay low for one
cycle of the new input clock (nominally) and then begin to follow the
new input clock. This is shown in Figure 1A.
CLK0
CLK1
CLK_SEL
Output
Figure 1A. CLK_SEL Timing Diagram
Another case is where one of the inputs was selected and running but
has since stopped (either high or low). If a CLK_SEL event happens
after a clock has stopped, the output change can take effect up to 1µs
after the input clock stopped. The output will go low and then follow
the second period of the new clock input. Figure 1B shows an
example of this.
CLK0
CLK1
CLK_SEL
Output
1µs
Figure 1B. CLK_SEL with Bad Input Timing Diagram
ICS854S1208AYI REVISION A APRIL 27, 2012
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©2012 Integrated Device Technology, Inc.