ICS854104 Datasheet, PDF(8/15 Page) Integrated Device Technology – Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer

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ICS854104 Datasheet, PDF (8/15 Pages) Integrated Device Technology – Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer

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ICS854104 Data Sheet

LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Application Information

Wiring the Differential Input to Accept Single-Ended Levels

Figure 1 shows how the differential input can be wired to accept

single-ended levels. The reference voltage V_REF = VDD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock swing

is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 =

0.609.

Single Ended Clock Input

V_REF

0.1u

VDD

CLK

nCLK

Figure 1. Single-Ended Signal Driving Differential Input

Recommendations for Unused Input and Output Pins

Inputs:

LVCMOS Control Pins

All control pins have internal pullups; additional resistance is not

required but can be added for additional protection. A 1kâ¦ resistor

can be used.

Outputs:

LVDS Outputs

All unused LVDS output pairs can be either left floating or terminated

with 100â¦ across. If they are left floating, there should be no trace

attached.

ICS854104AG REVISION A AUGUST 14, 2009

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