ICS854104 Datasheet, PDF (2/15 Pages) Integrated Device Technology – Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer

ICS854104 Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9, 10
11, 12
13, 14
15, 16
Name
OE0
OE1
OE2
V_DD
GND
CLK
nCLK
OE3
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Input
Input
Input
Power
Power
Input
Input
Input
Output
Output
Output
Output
Type
Pullup
Pullup
Pullup
Pulldown
Pullup/Pulldown
Pullup
Description
Output enable pin for Q0, nQ0 outputs. See Table 3. LVCMOS/LVTTL interface
levels.
Output enable pin for Q1, nQ1 outputs. See Table 3. LVCMOS/LVTTL interface
levels.
Output enable pin for Q2, nQ2 outputs. See Table 3. LVCMOS/LVTTL interface
levels.
Positive supply pin.
Power supply ground.
Non-inverting differential clock input.
Inverting differential clock input. V_DD/2 default when left floating.
Output enable pin for Q3, nQ3 outputs. See Table 3. LVCMOS/LVTTL interface
levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
R_PULLUP
R_PULLDOWN
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Function Table
Table 3. Output Enable Function Table
Inputs
Outputs
OE[3:0]
Q[0:3], nQ[0:3]
0
High-Impedance
1
Active (default)
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
ICS854104AG REVISION A AUGUST 14, 2009
2
©2009 Integrated Device Technology, Inc.