ICS854104 Datasheet, PDF (1/15 Pages) Integrated Device Technology – Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer

Low Skew, 1-to-4,
Differential-to-LVDS Fanout Buffer
ICS854104
DATA SHEET
General Description
The ICS854104 is a low skew, high performance
ICS
1-to-4 Differential-to-LVDS Clock Fanout Buffer and a
HiPerClockS™ _{member of the HiPerClockS™ family of High}
Performance Clock Solutions from IDT. Utilizing Low
Voltage Differential Signaling (LVDS), the ICS854104
provides a low power, low noise, solution for distributing clock signals
over controlled impedances of 100Ω. The ICS854104 accepts a
differential input level and translates it to LVDS output levels.
Guaranteed output and part-to-part skew characteristics make the
ICS854104 ideal for those applications demanding well defined
performance and repeatability.
Features
• Four differential LVDS output pairs
• One differential clock input pair
• CLK/nCLK can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Each output has an individual OE control
• Maximum output frequency: 700MHz
• Translates differential input signals to LVDS levels
• Additive phase jitter, RMS: 0.232ps (typical)
• Output skew: 50ps (maximum)
• Part-to-part skew: 350ps (maximum)
• Propagation delay: 1.3ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
CLK ^Pulldown
nCLK ^{Pullup/Pulldown}
Pullup
Q0
nQ0
OE0
Pullup
Pullup
Q1
nQ1
OE1
Q2
nQ2
OE2
Pullup
Q3
nQ3
OE3
ICS854104AG REVISION A AUGUST 14, 2009
Pin Assignment
OE0 1
OE1 2
OE2 3
V_DD 4
GND 5
CLK 6
nCLK 7
OE3 8
16 Q0
15 nQ0
14 Q1
13 nQ1
12 Q2
11 nQ2
10 Q3
9 nQ3
ICS854104
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
1
©2009 Integrated Device Technology, Inc.