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ICS843442I Datasheet, PDF (8/13 Pages) Integrated Device Technology – FemtoClock™ SAS/SATA Clock Generator | |||
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ICS843442I Data Sheet
FEMTOCLOCK⢠SAS/SATA Clock Generator
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups and pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k⦠resistor can be used.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50â¦
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
3.3V
Zo = 50â¦
3.3V
+
LVPECL
Zo = 50â¦
R1
50â¦
RTT =
1
((VOH + VOL) / (VCC â 2)) â 2
* Zo
_
Input
R2
50â¦
VCC - 2V
RTT
Figure 3A. 3.3V LVPECL Output Termination
3.3V
LVPECL
3.3V
R3
R4
125â¦
125â¦
3.3V
Zo = 50â¦
+
Zo = 50â¦
R1
84â¦
_
R2
84â¦
Input
Figure 3B. 3.3V LVPECL Output Termination
ICS843442AGI REVISION A JUNE 24, 2009
8
©2009 Integrated Device Technology, Inc.
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