ICS843442I Datasheet, PDF (2/13 Pages) Integrated Device Technology – FemtoClock™ SAS/SATA Clock Generator

ICS843442I Data Sheet
FEMTOCLOCK™ SAS/SATA Clock Generator
Table 1. Pin Descriptions
Number
1, 15
2,
3
4,
8
5, 6, 7
9
10, 11
12, 13
14
16
Name
V_EE
XTAL_OUT,
XTAL_IN
SSC_SEL0,
SSC_SEL1
nc
V_CC
Q1, nQ1
Q0, nQ0
nPLL_SEL
F_SEL
Type
Power
Input
Description
Negative supply pins.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Input
Unused
Power
Output
Output
Input
Input
Pulldown SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels.
Pulldown
Pullup
No connect.
Power supply pin.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
PLL Bypass pin. When LOW, selects PLL. When HIGH, bypasses PLL.
LVCMOS/LVTTL interface levels.
Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.
NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
R_PULLDOWN
R_PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
Function Tables
Table 3A. SSC_SEL[1:0] Function Table
Inputs
SSC_SEL1
SSC_SEL0
Mode
0 (default)
0 (default)
SSC Off
0
1
0.5% Down-spread
1
0
0.23% Down-spread
1
1
0.5% Center-spread
Table 3B. F_SEL Function Table
Input
F_SEL
Output Frequency
(MHz)
0
75
1 (default)
150
ICS843442AGI REVISION A JUNE 24, 2009
2
©2009 Integrated Device Technology, Inc.