ICS843442I Datasheet, PDF (7/13 Pages) Integrated Device Technology – FemtoClock™ SAS/SATA Clock Generator

ICS843442I Data Sheet
FEMTOCLOCK™ SAS/SATA Clock Generator
Application Information
Crystal Input Interface
The ICS843442I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in Figure
1 below were determined using a 25MHz, 18pF parallel resonant
crystal and were chosen to minimize the ppm error. The optimum C1
and C2 values can be slightly adjusted for different board layouts.
X1
18pF Parallel Crystal
XTAL_IN
C1
27p
XTAL_OUT
C2
27p
Figure 1. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 2. The XTAL_OUT pin can be left floating. The input
edge rate can be as slow as 10ns. For LVCMOS signals, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done in
one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1 and R2
can be 100Ω. This can also be accomplished by removing R1 and
making R2 50Ω. By overdriving the crystal oscillator, the device will
be functional, but note, the device performance is guaranteed by
using a quartz crystal.
VCC
VCC
R1
Ro
Rs
50Ω
0.1µf
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 2. General Diagram for LVCMOS Driver to XTAL Input Interface
ICS843442AGI REVISION A JUNE 24, 2009
7
©2009 Integrated Device Technology, Inc.