ICS840001I-25 Datasheet, PDF (8/12 Pages) Integrated Device Technology – FEMTOCLOCK LVCMOS LVTTL CLOCK GENERATOR

ICS840001I-25
FEMTOCLOCK™ LVCMOS/LVTTL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS840001I-25.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS840001I-25 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.
DD
Core and Output Power Dissipation
• Power (core, output) = V * (I + I ) = 3.465V * (83mA + 2mA) = 294.5mW
DD_MAX
DD
DDO
LVCMOS Output Power Dissipation
• Output Impedance R Power Dissipation due to Loading 50Ω to V /2
OUT
DDO
Output Current I_OUT = V_{DDO_MAX} / [2 * (50Ω + R_OUT)] = 3.465V / [2 * (50Ω + 15Ω)] = 26.6mA
• Power Dissipation on the R_OUT per LVCMOS output
Power (R_OUT) = R_OUT * (I_OUT)² = 15Ω * (26.6mA)² = 10.6mW per output
• Dynamic Power Dissipation at 156.25MHz
Power (156.25MHz) = C_PD * Frequency * (V_DDO)² = 6pF * 156.25MHz * (3.465V)² = 11.26mW per output
Total Power Dissipation
• Total Power
= Power (core, output) + Power Dissipation (R_OUT) + Dyamic Power Dissipation (156.25MHz)
= 294.5mW + 10.6mW + 11.26mW
= 316.4mW
IDT^™ / ICS^™ LVCMOS CLOCK GENERATOR
8
ICS840001BGI-25 REV. A MARCH 31, 2009