ICS840001I-25 Datasheet, PDF (3/12 Pages) Integrated Device Technology – FEMTOCLOCK LVCMOS LVTTL CLOCK GENERATOR

ICS840001I-25
FEMTOCLOCK™ LVCMOS/LVTTL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V_DD
4.6V
Inputs, V
I
-0.5V to V + 0.5 V
DD
Outputs, V_O
-0.5V to V_DDO + 0.5V
Package Thermal Impedance, θ_JA 129.5°C/W (0 mps)
Storage Temperature, T_STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V_DD = V_DDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
V_DD
V_DDO
I_DD
I_DDO
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
83
2
Units
V
V
mA
mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, V_DD = V_DDO =2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
V_DD
V_DDO
I_DD
I_DDO
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
80
2
Units
V
V
mA
mA
TABLE
3C.
LVCMOS/LVTTL
DC
CHARACTERISTICS,
V
DD
=
V
DDO
=
3.3V±5%
OR
2.5V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
V_IH
Input High Voltage
V_DD = 3.465V
2
V_DD = 2.625V
1.7
V_IL
Input Low Voltage
V_DD = 3.465V
-0.3
V_DD = 2.625V
-0.3
I_IH
Input High Current
REF_IN,
SEL_[0:2]
V_DD = V_IN = 3.465V or 2.625V
I
IL
Input Low Current
REF_IN,
SEL_[0:2]
V = 3.465V or 2.625V, V = 0V
DD
IN
-150
V_OH
Output High Voltage; NOTE 1
V_DDO = 3.465V
V_DDO = 2.625V
2.6
1.8
V_OL
Output Low Voltage; NOTE 1
V_DDO = 3.465V or 2.625V
NOTE 1: Outputs terminated with 50Ω to V_DDO/2. See Parameter Measurement Information Section,
"Output Load Test Circuit" diagrams.
V_DD + 0.3
V_DD + 0.3
0.8
0.7
5
0.6
Units
V
V
V
V
µA
µA
V
V
V
IDT^™ / ICS^™ LVCMOS CLOCK GENERATOR
3
ICS840001BGI-25 REV. A MARCH 31, 2009