9ZX21501B Datasheet, PDF (8/16 Pages) Integrated Device Technology – 15-Output Differential Zbuffer for PCIe Gen2/3 and QPI

9ZX21501B
15-Output Differential Zbuffer for PCIe Gen2/3 and QPI
Electrical Characteristics - Phase Jitter Parameters
TA = T_COM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
t_jphPCIeG1
t_jphPCIeG2
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
36
86
ps (p-p)
1.2
3
ps
(rms)
1.9
3.1
ps
(rms)
Jitter, Phase
t_jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.5
1
ps
(rms)
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
0.31
0.5
ps
(rms)
t_{jphQPI_SMI}
QPI & SMI
(100MHz, 8.0Gb/s, 12UI)
0.21
0.3
ps
(rms)
QPI & SMI
(100MHz, 9.6Gb/s, 12UI)
ps
0.17
0.2
(rms)
t_jphPCIeG1
t_jphPCIeG2
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
4
10
ps (p-p)
0.25
0.3
ps
(rms)
0.57
0.7
ps
(rms)
Additive Phase Jitter,
Bypass mode
t_jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
0.20
0.3
ps
(rms)
0.22
0.3
ps
(rms)
t_{jphQPI_SMI}
QPI & SMI
(100MHz, 8.0Gb/s, 12UI)
0.08
0.1
ps
(rms)
QPI & SMI
(100MHz, 9.6Gb/s, 12UI)
ps
0.08
0.1
(rms)
1 _{Applies to all outputs.}
2 _{See http://www.pcisig.com for complete specs}
3 _{Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.}
4 _{Subject to final radification by PCI SIG.}
5 _{Calculated from Intel-supplied Clock Jitter Tool v 1.6.3}
6 _{For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2}
Notes
1,2,3
1,2
1,2
1,2,4
1,5
1,5
1,5
1,2,3
1,2,6
1,2,6
1,2,4,6
1,5,6
1,5,6
1,5,6
Electrical Characteristics - Current Consumption
TA = T_COM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Operating Supply Current I_DD3.3OP All outputs active @100MHz, C_L = Full load;
Powerdown Current
I_DD3.3PDZ
All differential pairs tri-stated
1_{Guaranteed by design and characterization, not 100% tested in production.}
390
425
mA
1
5
15
mA
1
Power Management Table
Inputs
Control Bits/Pins
DIF_IN/
SMBus
DIF(5:8,10:12)/ Other DIF/
CKPWRGD•/PD#
DIF_IN#
EN bit OE# Pin DIF(5:8,10:12)# DIF#
0
X
X
X
Hi-Z¹
Hi-Z¹
0
X
Hi-Z¹
Hi-Z¹
1
Running
1
0
Running
Running
1
1
Hi-Z¹
Running
NOTE:
1. Due to external pull down resistors, HI-Z results in Low/Low on the True/Complement outputs
Outputs
DFB_OUT/
DFB_OUT#
Hi-Z¹
Running
Running
Running
PLL
State
OFF
ON
ON
ON
IDT^® 15-Output Differential Zbuffer for PCIe Gen2/3 and QPI
8
1629C - 12/15/11