9ZX21501B Datasheet, PDF (3/16 Pages) Integrated Device Technology – 15-Output Differential Zbuffer for PCIe Gen2/3 and QPI

9ZX21501B
15-Output Differential Zbuffer for PCIe Gen2/3 and QPI
Pin Description
PIN #
PIN NAME
1 IREF
2 100M_133M#
3 HIBW_BYPM_LOBW#
4 CKPWRGD_PD#
5 GND
6 VDDR
7 DIF_IN
8 DIF_IN#
9 SMB_A0_tri
10 SMBDAT
11 SMBCLK
12 SMB_A1_tri
13 DFB_IN
14 DFB_IN#
15 DFB_OUT#
16 DFB_OUT
17 DIF_0
18 DIF_0#
19 VDD
20 DIF_1
21 DIF_1#
22 DIF_2
23 DIF_2#
24 GND
25 DIF_4
26 DIF_4#
27 VDD
28 DIF_5
29 DIF_5#
30 OE5#
31 DIF_6
32 DIF_6#
33 OE6#
34 DIF_7
35 DIF_7#
36 OE7#
TYPE
OUT
IN
IN
IN
PWR
PWR
IN
IN
IN
I/O
IN
IN
IN
IN
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
DESCRIPTION
This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision
resistor to ground. 475ohm is the standard value for 100ohm differential impedance. Other impedances
require different values. See data sheet.
3.3V Input to select operating frequency
See Functionality Table for Definition
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
Notifies device to sample latched inputs and start up on first high assertion, or exit Power Down Mode on
subsequent assertions. Low enters Power Down Mode.
Ground pin.
3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and
filtered appropriately.
0.7 V Differential TRUE input
0.7 V Differential Complementary Input
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1 to decode 1 of 9
SMBus Addresses.
Data pin of SMBUS circuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0 to decode 1 of 9
SMBus Addresses.
True half of differential feedback input, provides feedback signal to the PLL for synchronization with the
input clock to elimate phase error.
Complementary half of differential feedback input, provides feedback signal to the PLL for synchronization
with input clock to elimate phase error.
Complementary half of differential feedback output, provides feedback signal to the PLL for
synchronization with input clock to eliminate phase error.
True half of differential feedback output, provides feedback signal to the PLL for synchronization with the
input clock to eliminate phase error.
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 5.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 7.
1 =disable outputs, 0 = enable outputs
IDT^® 15-Output Differential Zbuffer for PCIe Gen2/3 and QPI
3
1629C - 12/15/11