9ZX21501B Datasheet, PDF (2/16 Pages) Integrated Device Technology – 15-Output Differential Zbuffer for PCIe Gen2/3 and QPI

9ZX21501B
15-Output Differential Zbuffer for PCIe Gen2/3 and QPI
Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
IREF 1
48 OE11#
100M_133M# 2
47 DIF_11#
HIBW_BYPM_LOBW# 3
46 DIF_11
CKPWRGD_PD# 4
45 OE10#
GND 5
44 DIF_10#
VDDR 6
43 DIF_10
DIF_IN 7
42 NC
DIF_IN# 8
SMB_A0_tri 9
9ZX21501B
41 VDD
40 GND
SMBDAT 10
39 OE8#
SMBCLK 11
38 DIF_8#
SMB_A1_tri 12
37 DIF_8
DFB_IN 13
36 OE7#
DFB_IN# 14
35 DIF_7#
DFB_OUT# 15
34 DIF_7
DFB_OUT 16
33 OE6#
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64-pin MLF
Functionality at Power Up (PLL Mode)
100M_133M#
DIF_IN
(MHz)
1
100.00
0
133.33
DIF
MHz
DIF_IN
DIF_IN
PLL Operating Mode
HiBW_BypM_LoBW#
MODE
Low
PLL Lo BW
Mid
High
Bypass
PLL Hi BW
NOTE: PLL is OFF in Bypass Mode
PLL Operating Mode Readback Table
HiBW_BypM_LoBW# Byte0, bit 7
Low (Low BW)
0
Mid (Bypass)
0
High (High BW)
1
Byte 0, bit 6
0
1
1
Tri-level Input Thresholds
Level
Voltage
Low
<0.8V
Mid
1.2<Vin<1.8V
High
Vin > 2.2V
IDT^® 15-Output Differential Zbuffer for PCIe Gen2/3 and QPI
Power Connections
Pin Number
VDD
63
6
19, 27, 41,
52, 60
GND
64
5
24, 40, 55
Description
Analog PLL
Input Circuit
DIF clocks
9ZX21501 SMBus Addressing
Pin
SMBus Address
SMB_A1_tri SMB_A0_tri (Rd/Wrt bit = 0)
0
0
D8
0
M
DA
0
1
DE
M
0
C2
M
M
C4
M
1
C6
1
0
CA
1
M
CC
1
1
CE
1629C - 12/15/11
2