89HPES22H16 Datasheet, PDF (8/37 Pages) Integrated Device Technology – Low-latency cut-through switch architecture

IDT 89HPES22H16 Data Sheet
Signal
Type
Name/Description
GPIO[24]
GPIO[25]¹
GPIO[26]
GPIO[27]
GPIO[28]
GPIO[29]
GPIO[30]
GPIO[31]
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN3
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 3
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN4
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 4
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN5
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 5
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN6
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 6
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN7
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 7
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN10
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 10
Table 4 General Purpose I/O Pins (Part 4 of 4)
1. _{GPIO pins 22 and 25 are not available in the 23x23mm package.}
Signal
CCLKDS
CCLKUS
MSMBSMODE
Type
Name/Description
I Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a
common clock is being used between the downstream device and the downstream
port.
I Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a
common clock is being used between the upstream device and the upstream port.
I Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus
should operate at 100 KHz instead of 400 KHz. This value may not be overridden.
Table 5 System Pins (Part 1 of 2)
8 of 37
October 3, 2011