89HPES22H16 Datasheet, PDF (14/37 Pages) Integrated Device Technology – Low-latency cut-through switch architecture

IDT 89HPES22H16 Data Sheet
Logic Diagram — PES22H16
Reference
Clock
4
PEREFCLKP[3:0]
4
PEREFCLKN[3:0]
REFCLKM
PCI Express
Switch
SerDes Input
Port 0
PE0RP[0]
PE0RN[0]
PE0RP[3]
PE0RN[3]
PCI Express
Switch
SerDes Input
Port 1
PE1RP[0]
PE1RN[0]
PCI Express
Switch
SerDes Input
Port 2
PCI Express
Switch
SerDes Input
Port 3
PE2RP[0]
PE2RN[0]
PE2RP[3]
PE2RN[3]
PE3RP[0]
PE3RN[0]
PCI Express
Switch
SerDes Input
Port 15
PE15RP[0]
PE15RN[0]
PES22H16
PE0TP[0]
PE0TN[0]
PE0TP[3]
PE0TN[3]
PE1TP[0]
PE1TN[0]
PE2TP[0]
PE2TN[0]
PE2TP[3]
PE2TN[3]
PE3TP[0]
PE3TN[0]
PE15TP[0]
PE15TN[0]
PCI Express
Switch
SerDes Output
Port 0
PCI Express
Switch
SerDes Output
Port 1
PCI Express
Switch
SerDes Output
Port 2
PCI Express
Switch
SerDes Output
Port 3
PCI Express
Switch
SerDes Output
Port 15
4
Master
SMBus Interface
MSMBADDR[4:1]
MSMBCLK
MSMBDAT
System
Pins
MSMBSMODE
CCLKDS
CCLKUS
RSTHALT
PERSTN
4
SWMODE[3:0]
4
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
Slave
SMBus Interface
32
GPIO[31:0]
General Purpose
I/O
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
JTAG Pins
V_DDCORE
V_DDIO
V_DDPE
V_DDAPE
V_SS
V_TTPE
Power/Ground
Figure 4 PES22H16 Logic Diagram
Note: GPIO pins 22 and 25 are not available in the 23x23mm package.
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October 3, 2011