89HPES22H16 Datasheet, PDF (1/37 Pages) Integrated Device Technology – Low-latency cut-through switch architecture

22-Lane 16-Port
PCI Express® Switch
®
89HPES22H16
Data Sheet
Device Overview
The 89HPES22H16 is a member of the IDT PRECISE™ family of
PCI Express® switching solutions. The PES22H16 is a 22-lane, 16-port
peripheral chip that performs PCI Express packet switching with a
feature set optimized for high-performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and up to
fifteen downstream ports and supports switching between downstream
ports.
Features
◆ _{High Performance PCI Express Switch}
– Sixteen maximum switch ports
• Two x4 ports
• Fourteen x1 ports
– Twenty-two 2.5 Gbps embedded SerDes
• Supports pre-emphasis and receive equalization on per-port
basis
– Delivers 88 Gbps (11 GBps) of aggregate switching capacity
– Low-latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– Supports two virtual channels and eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
◆ _{Flexible Architecture with Numerous Configuration Options}
– Port arbitration schemes utilizing round robin algorithms
– Automatic per port link width negotiation from x4 to x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Supports locked transactions, allowing use with legacy soft-
ware
– Ability to load device configuration from serial EEPROM
– Ability to control device via SMBus
◆ _{Highly Integrated Solution}
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates twenty-two 2.5 Gbps embedded full duplex SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
◆ _{Reliability, Availability, and Serviceability (RAS) Features}
– Redundant upstream port failover capability
– Supports optional PCI Express end-to-end CRC checking
Block Diagram
x4/x2/x1
x4/x2/x1
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
Route Table
Frame Buffer
16-Port Switch Core
Port
Arbitration
Scheduler
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
.......
DL/Transaction Layer
SerDes
x1
x1
x1
22 PCI Express Lanes
2 x4 ports and 14 x1 Ports
Figure 1 Internal Block Diagram
 2011 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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October 3, 2011