82P33810 Datasheet, PDF (8/13 Pages) Integrated Device Technology – Composite clock inputs

82P33810 SHORT FORM DATA SHEET
Table 1: Pin Description (Continued)
Pin No.
Name
I/O
Type
Description
SDO: Serial Data Output
In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked
SDO/I2C_SDA/
out of the device on the active edge of SCLK.
C5
UART_TX
I2C_SDA
I/O
CMOS/
Open Drain
I2C_SDA: Serial Data Input/Output
In I2C mode, this pin is used as the input/output for the serial data.
UART_TX:
In UART mode, this pin is used as the transmit data (UART Transmit)
JTAG (per IEEE 1149.1)
F1
TMS
I
pull-up
CMOS
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK.
K3
TRSTB
I
pull-down
CMOS
TRSTB: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
TCK: JTAG Test Clock
G1
TCK
I
pull-down
CMOS
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely
retain their state.
L3
TDI
I
pull-up
CMOS
TDI: JTAG Test Data Input
The test data are input on this pin. They are clocked into the device on the rising edge of
TCK.
TDO: JTAG Test Data Output
L5
TDO
O
tri-state
CMOS
The test data are output on this pin. They are clocked out of the device on the falling edge of
TCK.
TDO pin outputs a high impedance signal except during the process of data scanning.
Power & Ground
C1, C6, C7, D2, F2, F9,
G2, H2, K1, K2
A5, A7, B2, B3, L4, M4
E4, E6, L7, M8
D5,F7
L10, H12
B9, C2, D1, D6, D7, E2,
E8, F3, F8, H3, L1, L2
B1, B4, B5, B7, K4, M3
E7, F4, K7, M7
D4, F6, H11, L9
D3
C3, F5, G4, G5, G6, G8,
H4, H5, H6, H7, H8, J3,
J4, J5, J6, J7, J8
VDDA
VDDAO
VDDDO
VDDD
VDDD_1_8
VSSA
VSSAO
VSSDO
VSSD
VSSCOM
VSS
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
Ground
Ground
-
VDDA: Analog Core Power - +3.3V DC nominal
VDDAO: Analog Output Power - +3.3V DC nominal
VDDDO: Digital Output Power - +3.3V DC nominal
VDDD: Digital Core Power - +3.3V DC nominal
VDDD_1_8: Digital Core Power - +1.8V DC nominal
-
VSSA: Ground
VSSAO: Ground
VSSDO: Ground
VSSD: Ground
-
VSSCOM: Ground
VSS: Ground
-
Other
A1, A2, A3, A4, A10,
A12, B10, B12, E3, G3,
IC
G7, L6
IC: Internal Connection
-
-
Internal Use. This pin must be left open for normal operation.
SYNCHRONIZATION MANAGEMENT UNIT FOR IEEE 1588 AND SYNCHRONOUS ETHERNET
8
REVISION 2 12/08/14