82P33810 Datasheet, PDF (7/13 Pages) Integrated Device Technology – Composite clock inputs

82P33810 SHORT FORM DATA SHEET
Table 1: Pin Description (Continued)
Pin No.
G9
H9
J9
B11
C11
D9
Name
DPLL2_LOCK
DPLL1_LOCK
INT_REQ
MPU_MODE1/
I2CM_SCL
MPU_MODE0/
I2CM_SDA
SDI/I2C_AD2/
UART_RX
I/O
O
O
O
Tri-state
I/O
pull-down
I
pull-down
Type
Description
CMOS
CMOS
DPLL2_LOCK
This pin goes high when DPLL2 is locked
DPLL1_LOCK
This pin goes high when DPLL1 is locked
Microprocessor Interface
CMOS
INT_REQ: Interrupt Request
This pin is used as an interrupt request.
MPU_MODE[1:0]: Microprocessor Interface Mode Selection
During reset, these pins determine the default value of the MPU_SEL_CNFG[1:0] bits as fol-
lows:
00: I2C mode
CMOS/
Open Drain
01: SPI mode
10: UART mode
11: I2C master (EEPROM) mode
I2CM_SCL: Serial Clock Line
In I2C master mode, the serial clock is output on this pin.
I2CM_SDA: Serial Data Input for I2C Master Mode
In I2C master mode, this pin is used as the for the serial data.
SDI: Serial Data Input
In Serial mode, this pin is used as the serial data input. Address and data on this pin are seri-
ally clocked into the device on the rising edge of SCLK.
CMOS I2C_AD2: Device Address Bit 2
In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.
UART_RX
In UART mode, this pin is used as the receive data (UART Receive)
CLKE: SCLK Active Edge Selection
In Serial mode, this pin is an input, it selects the active edge of SCLK to update the SDO:
E5
CLKE/I2C_AD1
I
pull-down
CMOS
High - The falling edge;
Low - The rising edge.
I2C_AD1: Device Address Bit 1
In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.
CS: Chip Selection
In Serial modes, this pin is an input.A transition from high to low must occur on this pin for
C8
CS/I2C_AD0
I
pull-up
CMOS ^{each read or write operation and this pin should remain low until the operation is over.}
I2C_AD0: Device Address Bit 0
In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.
SCLK: Shift Clock
In Serial mode, a shift clock is input on this pin.
Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated
D10
SCLK/I2C_SCL
I
CMOS on the active edge of SCLK. The active edge is determined by the CLKE.
I2C_SCL: Serial Clock Line
In I2C mode, the serial clock is input on this pin.
REVISION 2 12/08/14
7
SYNCHRONIZATION MANAGEMENT UNIT FOR IEEE 1588 AND SYNCHRONOUS ETHERNET