82P33810 Datasheet, PDF (4/13 Pages) Integrated Device Technology – Composite clock inputs

82P33810 SHORT FORM DATA SHEET
1
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
A
IC
IC
IC
IC
VDDAO OUT5_POS VDDAO OUT6_POS
CAP2
SONET/SDH/LO
IC
S3
IC
A
B
VSSAO
VDDAO
VDDAO
VSSAO
VSSAO OUT5_NEG VSSAO OUT6_NEG
VSSA
IC
MPU_MODE1/I
IC
2CM_SCL
B
C
VDDA
D
VSSA
VSSA
VSS
OUT7 ^SDO/I2C_SD VDDA
A/UART_TX
VDDA
VSSCOM
VSSD
VDDD
VSSA
VDDA CS/I2C_AD0 CAP1
OUT8
MPU_MODE0/I Mfrsync_2K_
2CM_SDA
1PPS
C
VSSA
CAP3
SDI/I2C_AD2 SCLK/I2C_SC
/UART_RX
L
OUT11
OUT10
D
E
OSCI
VSSA
IC
VDDDO
CLKE/I2C_AD
1
VDDDO
VSSDO
VSSA DPLL3_LOCK IN14
IN13
Frsync_8K_1PP
S
E
F
TMS
VDDA
VSSA
VSSDO
VSS
VSSD
VDDD
VSSA
VDDA
IN12
IN8_NEG
IN8_POS
F
G
TCK
VDDA
IC
VSS
VSS
VSS
IC
VSS DPLL2_LOCK IN11
IN7_NEG
IN7_POS
G
H
xo_freq0/
LOS0
VDDA
VSSA
VSS
VSS
VSS
VSS
VSS DPLL1_LOCK IN10
VSSD
VDDD_1_8
H
J
xo_freq1/ xo_freq2/
LOS1
LOS2
VSS
VSS
VSS
VSS
VSS
VSS
INT_REQ
IN9
IN6_NEG
IN6_POS
J
K
VDDA
VDDA
TRSTB
VSSAO
OUT2
RSTB
VSSDO
MS_SL
IN2
IN1
IN5_NEG
IN5_POS
K
L
VSSA
VSSA
TDI
VDDAO
TDO
IC
VDDDO
OUT1
VSSD VDDD_1_8 IN4_NEG
IN4_POS
L
M ^{OUT4_POS OUT4_NEG VSSAO}
VDDAO OUT3_POS OUT3_NEG VSSDO
VDDDO OUT9_POS OUT9_NEG IN3_NEG
IN3_POS
M
1
2
3
4
5
6
7
8
9
10
11
12
Figure 2. Pin Assignment (Top View)
SYNCHRONIZATION MANAGEMENT UNIT FOR IEEE 1588 AND SYNCHRONOUS ETHERNET
4
REVISION 2 12/08/14