DAC1208D650 Datasheet, PDF (74/96 Pages) NXP Semiconductors – Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface

Integrated Device Technology
DAC1208D650
2, 4 or 8 interpolating DAC with JESD204A interface
Table 132. FLAG_CNT_MSB_LN3 register (address 17h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7 to 0 FLAG_CNT_LN3[15:8]
R
-
MSBs of flag_counter lane 3
Table 133. BER_LEVEL_LSB register (address 18h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7 to 0 BER_LEVEL[7:0]
R/W
00h
LSBs level used for simple (DC) BER-measurement
Table 134. BER_LEVEL_MSB register (address 19h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7 to 0 BER_LEVEL[15:8]
R/W
00h
MSBs level used for simple (DC)
BER-measurement
Table 135. INTR_ENA register (address 1Ah) bit description
Bit
Symbol
Access Value
7
INTR_ENA_NIT
R/W
0
1
6
INTR_ENA_DISP
R/W
0
1
5
INTR_ENA_KOUT
R/W
0
1
4
INTR_ENA_KOUT_UNEXP
R/W
0
1
3
INTR_ENA_K28_7
2
INTR_ENA_K28_5
1
INTR_ENA_K28_3
0
INTR_ENA_MISC
R/W
0
1
R/W
0
1
R/W
0
1
R/W
0
1
Description
not-in-table interrupt
no action
nit-error in ln<x> affects i_ln<x>
disparity-error interrupt
no action
disparity-error in ln<x> affects i_ln<x>
K-character interrupt
no action
detection k-control character in ln<x> affects
i_ln<x>
unexpected K-character interrupt
no action
detection unexpected K-character in ln<x> affects
i_ln<x>
K28_7 interrupt
no action
detection K28_7 in ln<x> affects i_ln<x>
K28_5 interrupt
no action
detection K28_5 in ln<x> affects i_ln<x>
K28_3 interrupt
no action
detection K28_3 in ln<x> affects i_ln<x>
miscellaneous interrupt
no action
detection depends on intr_misc_ena
(see Table 124)
DAC1208D650 4
Product data sheet
Rev. 04 — 2 July 2012
© IDT 2012. All rights reserved.
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