DAC1208D650 Datasheet, PDF (53/96 Pages) NXP Semiconductors – Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface

Integrated Device Technology
DAC1208D650
2, 4 or 8 interpolating DAC with JESD204A interface
Table 62. RST_EXT_FCLK register (address 04h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7 to 0 RST_EXT_FCLK_TIME[7:0]
R/W
3Fh
specifies extension time reset_fclk in f_clk periods
Table 63. RST_EXT_DCLK register (address 05h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7 to 0 RST_EXT_DCLK_TIME[7:0]
R/W
20h
specifies extension time reset_dclk (in dclk-periods)
Table 64. DCSMU_PREDIVCNT register (address 06h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7 to 0 DCSMU_PREDIVIDER[7:0]
R/W
1Eh
value used by dcsmu predivider (at f_clk)
Table 65. PLL_CHARGETIME register (address 07h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7 to 0 PLL_CHARGE_TIME[7:0]
R/W
32h
PLL charge time
(at f_clk/DCSMU_PREDIVIDER[7:0])
Table 66. PLL_RUN_IN_TIME register (address 08h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7 to 0 PLL_RUNIN_TIME[7:0]
R/W
32h
PLL run in time (at f_clk/DCSMU_PREDIVIDER[7:0])
Table 67. CA_RUN_IN_TIME register (address 09h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7 to 0 CA_RUNIN_TIME[7:0]
R/W
04h
clock alignment run in time
(at f_clk/DCSMU_PREDIVIDER[7:0])
Table 68. SET_VCM_VOLTAGE register (address 16h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
3 to 0 SET_VCM[3:0]
R/W
02h
set lane common-mode voltage (see Table 75)
Table 69. SET_SYNC register (address 17h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
6 to 4 SET_SYNC_VCOM[2:0]
R/W
4h
2 to 0 SET_SYNC_LEVEL[2:0]
R/W
3h
Description
set synchronization transmitter common-mode level
(see Table 76)
set synchronization transmitter output level swing
(see Table 77)
DAC1208D650 4
Product data sheet
Rev. 04 — 2 July 2012
© IDT 2012. All rights reserved.
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