DAC1208D650 Datasheet, PDF (58/96 Pages) NXP Semiconductors – Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface

Integrated Device Technology
DAC1208D650
2, 4 or 8 interpolating DAC with JESD204A interface
10.15.2.8 Page 4 bit definition detailed description
Please refer to Table 78 for a register overview and their default values. In the following
tables, all the values emphasized in bold are the default values.
Table 79. SR_DLP_0 register (address 00h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7
SR_SWA_LN3
R/W
0
6
SR_SWA_LN2
R/W
0
5
SR_SWA_LN1
R/W
0
4
SR_SWA_LN0
R/W
0
3
SR_CA_LN3
R/W
0
2
SR_CA_LN2
R/W
0
1
SR_CA_LN1
R/W
0
0
SR_CA_LN0
R/W
0
Description
soft reset sync_word_alignment lane 3
soft reset sync_word_alignment lane 2
soft reset sync_word_alignment lane 1
soft reset sync_word_alignment lane 0
soft reset clock_alignment lane 3
soft reset clock_alignment lane 2
soft reset clock_alignment lane 1
soft reset clock_alignment lane 0
Table 80. SR_DLP_1 register (address 01h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7
SR_CNTRL_LN3
R/W
0
6
SR_CNTRL_LN2
R/W
0
5
SR_CNTRL_LN1
R/W
0
4
SR_CNTRL_LN0
R/W
0
3
SR_DEC_LN3
R/W
0
2
SR_DEC_LN2
R/W
0
1
SR_DEC_LN1
R/W
0
0
SR_DEC_LN0
R/W
0
Description
soft reset controller lane 3
soft reset controller lane 2
soft reset controller lane 1
soft reset controller lane 0
soft reset decoder_10b8b lane 3
soft reset decoder_10b8b lane 2
soft reset decoder_10b8b lane 1
soft reset decoder_10b8b lane 0
Table 81. FORCE_LOCK register (address 02h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7
FORCE_LOCK_LN3
R/W
0
1
6
FORCE_LOCK_LN2
R/W
0
1
5
FORCE_LOCK_LN1
R/W
0
1
4
FORCE_LOCK_LN0
R/W
0
1
Description
lane 3 lock mode
automatic lock sync_word_alignment lane 3
manual lock sync_word_alignment lane 3
lane 2 lock mode
automatic lock sync_word_alignment lane 2
manual lock sync_word_alignment lane 2
lane 1 lock mode
automatic lock sync_word_alignment lane 1
manual lock sync_word_alignment lane 1
lane 0 lock mode
automatic lock sync_word_alignment lane 0
manual lock sync_word_alignment lane 0
DAC1208D650 4
Product data sheet
Rev. 04 — 2 July 2012
© IDT 2012. All rights reserved.
58 of 96