DAC1208D650 Datasheet, PDF (41/96 Pages) NXP Semiconductors – Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface

Integrated Device Technology
DAC1208D650
2, 4 or 8 interpolating DAC with JESD204A interface
Table 19. TXCFG register (address 01h) bit description …continued
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
1 to 0 INT_FIR[1:0]
R/W
interpolation
00
no interpolation
01
2
10
4
11
8
Table 20. PLLCFG register (address 02h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7
PLL_PD
R/W
0
1
6
-
R/W
0
5
-
R/W
0
4 to 3 PLL_DIV[1:0]
R/W
00
01
10
2 to 1 PLL_PHASE[1:0]
R/W
00
01
10
11
0
PLL_POL
R/W
0
1
Description
PLL
switched on
switched off
undefined
must be written with ’0’
PLL divider factor
2
4
8
PLL phase shift of f_s
0
120
240
undefined
clock edge of DAC (f_s)
normal
inverted
Table 21. FREQNCO_LSB register (address 03h) bit description
Bit
Symbol
Access Value Description
7 to 0 FREQ_NCO[7:0]
R/W
66h
lower 8 bits for the NCO frequency setting
Table 22. FREQNCO_LISB register (address 04h) bit description
Bit
Symbol
Access Value Description
7 to 0 FREQ_NCO[15:8]
R/W
66h
lower intermediate 8 bits for the NCO frequency
setting
Table 23. FREQNCO_UISB register (address 05h) bit description
Bit
Symbol
Access Value Description
7 to 0 FREQ_NCO[23:16]
R/W
66h
upper intermediate 8 bits for the NCO frequency
setting
DAC1208D650 4
Product data sheet
Rev. 04 — 2 July 2012
© IDT 2012. All rights reserved.
41 of 96