ICS87951I Datasheet, PDF (7/14 Pages) Integrated Device Technology – LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER

ICS87951I
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
V_DDA,
V_DDO
LVCMOS
GND
-1.65V±5%
SCOPE
Qx
V_DD
nCLK1
V
PP
CLK1
Cross Points
V
CMR
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
QA,
QB,
QCx,
QDx
V
DDO
2
V
DDO
2
V
DDO
2
Qx
tcycle n
➤
tcycle n+1
➤
tjit(cc) = tcycle n –tcycle n+1
Qy
1000 Cycles
V
DDO
2
V
DDO
2
t sk(o)
CYCLE-TO-CYCLE JITTER
OUTPUT SKEW
2V
0.8V
Clock
Outputs
t_R
2V
0.8V
t_F
nCLK1
CLK0,
CLK1
EXT_FB
➤ t(Ø)
V_OH
V_OL
V_OH
V_DDO
2
V_OL
OUTPUT RISE/FALL TIME
QA,
QB,
QCx,
QDx
V_DDO
2
t _PW
V_DDO
2
t _PERIOD
odc = ^{t PW}
t _PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
87951AYI
V_DDO
2
tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
PHASE JITTER AND STATIC PHASE OFFSET
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7
REV. C JULY 17, 2010