ICS87951I Datasheet, PDF (6/14 Pages) Integrated Device Technology – LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER

ICS87951I
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER
TABLE
5.
PLL
INPUT
REFERENCE
CHARACTERISTICS,
V =V =
DDA
DDO
3.3V±5%,
TA
=
-40°C
TO
85°C
Symbol
Parameter
Test Conditions
Minimum Typical
f_REF
Input Reference Frequency
Maximum Units
100
MHz
TABLE 6. AC CHARACTERISTICS, V_DDA = V_DDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
QA ÷2
180
f_MAX
Output Frequency
QA/QB ÷4
120
QB ÷8
60
f
PLL VCO Lock Range
VCO
200
480
CLK0
-185
15
165
t(Ø)
Static Phase Offset;
NOTE 1,3
CLK1,
fREF = 50MHz_,
Feedback = VCO/8
nCLK1
-445
-265
-95
Same Frequencies
375
tsk(o)
tjit(cc)
Output Skew; NOTE 2, 3
Cycle-to-Cycle Jitter; NOTE 3
Different Frequencies
QAf_MAX < 150MHz
QAf_MAX > 150MHz
500
750
±100
t_LOCK
PLL Lock Time; NOTE 3
10
t_R
Output Rise Time
0.8 to 2V
0.1
1.0
t_F
Output Fall Time
0.8 to 2V
0.1
1.0
t_PW
Output Pulse Width
tcycle/2 - 1000
tcycle/2 + 1000
t_PZL
Output Enable Time
6
t_PLZ, t_PHZ Output Disable Time
7
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Defined as the time difference between the input reference clock and the averaged feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
mS
ns
ns
ps
ns
ns
87951AYI
www.idt.com
6
REV. C JULY 17, 2010