ICS87951I Datasheet, PDF (3/14 Pages) Integrated Device Technology – LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER

ICS87951I
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
2
3
4
5
6
7, 13, 17,
21, 25, 29
8
V_DDA
EXT_FB
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
GND
CLK1
Power
Input
Input
Input
Input
Input
Analog supply pin.
Pullup
Feedback input to phase detector for regenerating clocks with
"zero delay". LVCMOS / LVTTL interface levels.
Pulldown
Selects divide value for Bank A output as described in Table 3D.
LVCMOS / LVTTL interface levels.
Pulldown
Selects divide value for Bank B output as described in Table 3D.
LVCMOS / LVTTL interface levels.
Pulldown
Selects divide value for Bank C outputs as described in Table 3D.
LVCMOS / LVTTL interface levels.
Pulldown
Selects divide value for Bank D outputs as described in Table 3D.
LVCMOS / LVTTL interface levels.
Power
Power supply ground.
Input Pullup Non-inverting differential clock input.
9
nCLK1
Input Pulldown Inverting differential clock input.
10
MR/nOE
11, 15,
19, 23, 27
12, 14,
16, 18, 20
V_DDO
QD4, QD3,
QD2, QD1, QD0
22, 24
QC1, QC0
26
QB
28
QA
Input
Power
Output
Output
Output
Output
Active HIGH Master Reset. Active LOW output enable. When logic
Pulldown
HIGH, the internal dividers are reset and the outputs are tri-stated
(HiZ). When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
Output supply pins.
Bank D clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Bank C clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Bank B clock output. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Bank A clock output. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
30
CLK0
Input Pulldown LVCMOS / LVTTL phase detector reference clock input.
Selects between the PLL and the reference clock as the input to the
31
PLL_SEL
Input Pulldown dividers. When HIGH, selects PLL. When LOW, selects the reference
clock. LVCMOS / LVTTL interface levels.
32
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects CLK0. When LOW,
selects CLK1, nCLK1. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
C_PD
R
PULLUP
R_PULLDOWN
R_OUT
Parameter
Input Capacitance
Power Dissipation Capacitance (per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
V_DDA, V_DDO = 3.47V
Minimum Typical Maximum Units
4
pF
25
pF
51
KΩ
51
KΩ
5
7
12
Ω
87951AYI
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3
REV. C JULY 17, 2010