ICS87951I Datasheet, PDF (1/14 Pages) Integrated Device Technology – LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER

ICS87951I
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER
GENERAL DESCRIPTION
The ICS87951I is a low voltage, low skew 1-to-9
Differential-to-LVCMOS/LVTTL Cock Generator. The
CS87951I has two selectable clock inputs. The single ended
clock input accepts LVCMOS or LVTTL input
levels. The CLK1, nCLK1 pair can accept most standard
differential input levels. With output frequencies up to 180MHz,
the ICS87951I is targeted for high performance clock appli-
cations. Along with a fully integrated PLL, the ICS87951I con-
tains frequency configurable outputs and an external
feedback input for regenerating clocks with “zero delay”.
FEATURES
• Fully integrated PLL
• Nine single ended 3.3V LVCMOS/LVTTL outputs
• Selectable single ended CLK0 or differential
CLK1, nCLK1 inputs
• The single ended CLK0 input can accept the following
input levels: LVCMOS or LVTTL input levels
• CLK1, nCLK1 supports the following input types:
LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Output frequency range: 25MHz to 180MHz
• VCO range: 200MHz to 480MHz
• External feedback for ”zero delay” clock regeneration
• Cycle-to-cycle jitter: ±100ps (typical)
• Output skew: 375ps (maximum)
• PLL reference zero delay: 350ps window (maximum)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
PIN ASSIGNMENT
VDDA
EXT_FB
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
GND
CLK1
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
ICS87951I
21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
QC0
VDDO
QC1
GND
QD0
VDDO
QD1
GND
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
87951AYI
www.idt.com
1
REV. C JULY 17, 2010