ICS859S0424I Datasheet, PDF (7/24 Pages) Integrated Device Technology – Four programmable differential LVPECL or LVDS output pairs

ICS859S0424I Data Sheet
4:4 DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
AC Electrical Characteristics
Table 6A. LVPECL AC Characteristics, V_CC = V_{CC_TAP} = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
f_OUT
t_PD
tjit
Output Frequency
Propagation Delay; NOTE 1
400
Buffer Additive Phase Jitter, RMS;
NOTE 2
100MHz, Integration Range:
12kHz – 20MHz
tsk(b)
Bank Skew; NOTE 3, 4
tsk(pp)
Part-to-Part Skew; NOTE 4, 5
tsk(o)
Output Skew; NOTE 4, 6
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
50
46
MUX_ISOLATION MUX Isolation
ƒOUT < 1.2GHz
Typical
0.22
45
Maximum
3
800
0.28
25
100
25
245
54
Units
GHz
ps
ps
ps
ps
ps
ps
%
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters are measured at ƒOUT ≤ 1.5GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Measured on Agilent E5052A Signal Source Analyzer. Refer to Additive Phase Jitter section.
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Defined as skew between outputs on different devices operating a the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of input on each device, the output is measured at the differential cross points.
NOTE 6: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
Table 6B. LVPECL AC Characteristics, V_CC = V_{CC_TAP} = 2.5V ± 5%, T_A = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
f_OUT
t_PD
tjit
Output Frequency
Propagation Delay; NOTE 1
400
Buffer Additive Phase Jitter, RMS;
NOTE 2
100MHz, Integration Range:
12kHz – 20MHz
tsk(b)
Bank Skew; NOTE 3, 4
tsk(pp)
Part-to-Part Skew; NOTE 4, 5
tsk(o)
Output Skew; NOTE 4, 6
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
50
46
MUX_ISOLATION MUX Isolation
ƒOUT < 1.2GHz
Typical
0.22
45
Maximum
3
800
0.28
25
100
25
235
54
Units
GHz
ps
ps
ps
ps
ps
ps
%
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters are measured at ƒOUT ≤ 1.5GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Measured on Agilent E5052A Signal Source Analyzer. Refer to Additive Phase Jitter section.
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Defined as skew between outputs on different devices operating a the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of input on each device, the output is measured at the differential cross points.
NOTE 6: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
ICS859S0424BGI REVISION A OCTOBER 12, 2011
7
©2011 Integrated Device Technology, Inc.