ICS859S0424I Datasheet, PDF (2/24 Pages) Integrated Device Technology – Four programmable differential LVPECL or LVDS output pairs

ICS859S0424I Data Sheet
4:4 DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
Table 2. Pin Descriptions
Number
Name
Type
Description
1,
2
CLK_SEL0,
CLK_SEL1
Input
Pulldown Clock select inputs. See Table 4A. LVCMOS / LVTTL interface levels.
3
PCLK0
Input Pulldown Non-inverting differential LVPECL clock input.
4
nPCLK0
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
5
PCLK1
Input Pulldown Non-inverting differential clock input.
6
nPCLK1
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
7
PCLK2
Input Pulldown Non-inverting differential clock input.
8
nPCLK2
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
9
PCLK3
Input Pulldown Non-inverting differential clock input.
10
nPCLK3
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
11
OEA
Input
Pullup
Output enable pin for Bank A outputs. See Table 4B.
LVCMOS/LVTTL interface levels.
12
OEB
Input
Pullup
Output enable pin for Bank B outputs. See Table 4B.
LVCMOS/LVTTL interface levels.
13
SEL_OUT
Input
Pullup
Output select pin. When LOW, selects LVDS levels. When HIGH, selects
LVPECL levels. LVCMOS/LVTTL interface levels. See Table 1B.
14
15, 16
V_{CC_TAP}
nQB1, QB1
Power
Output
Power supply pin. See Table 1A.
Differential output pair. LVPECL or LVDS interface levels.
17, 18
nQB0, QB0 Output
Differential output pair. LVPECL or LVDS interface levels.
19, 20
nQA1, QA1 Output
Differential output pair. LVPECL or LVDS interface levels.
21, 22
nQA0, QA0 Output
Differential output pair. LVPECL or LVDS interface levels.
23
V_EE
Power
24
V_CC
Power
Negative supply pin.
Power supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 3. Pin Characteristics
Symbol
C_IN
R_PULLUP
R_PULLDOWN
R_VCC/2
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Input Pullup/Pulldown Resistor
Test Conditions
Minimum
Typical
2
51
51
50
Maximum
Units
pF
kΩ
kΩ
kΩ
ICS859S0424BGI REVISION A OCTOBER 12, 2011
2
©2011 Integrated Device Technology, Inc.